binutils-gdb/sim/example-synacor
Mike Frysinger 2662c237a9 sim: regen against sim/m4/
My scripts weren't updated to use new -I../m4 as the first arg.
2021-04-21 20:40:51 -04:00
..
aclocal.m4 sim: regen against sim/m4/ 2021-04-21 20:40:51 -04:00
ChangeLog sim: regen against sim/m4/ 2021-04-21 20:40:51 -04:00
config.in
configure sim: use -Werror when probing for supported warning flags 2021-04-21 19:48:35 -04:00
configure.ac
interp.c
Makefile.in
README
README.arch-spec
sim-main.c
sim-main.h

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.