binutils-gdb/gdb/features
Andrew Burgess 172fb711a2 gdb/riscv: Use legacy register numbers in default target description
When the target description support was added to RISC-V, the register
numbers assigned to the fflags, frm, and fcsr control registers in the
default target descriptions didn't match the register numbers used by
GDB before the target description support was added.

What this means is that if a tools exists in the wild that is using
hard-coded register number, setup to match GDB's old numbering, then
this will have been broken (for fflags, frm, and fcsr) by the move to
target descriptions.  QEMU is such a tool.

There are a couple of solutions that could be used to work around this
issue:

 - The user can create their own xml description file with the
   register numbers setup to match their old tool, then load this by
   telling GDB 'set tdesc filename FILENAME'.

 - Update their old tool to use the newer default numbering scheme, or
   better yet add proper target description support to their tool.

 - We could have RISC-V GDB change to maintain the old defaults.

This patch changes GDB back to using the old numbering scheme.

This change is only visible to remote targets that don't supply their
own xml description file and instead rely on GDB's default numbering.

Note that even though 32bit-cpu.xml and 64bit-cpu.xml have changed,
the corresponding .c file has not, this is because the numbering added
to the registers in the xml files is number 0, this doesn't result in
any new C code being generated .

gdb/ChangeLog:

	* features/riscv/32bit-cpu.xml: Add register numbers.
	* features/riscv/32bit-fpu.c: Regenerate.
	* features/riscv/32bit-fpu.xml: Add register numbers.
	* features/riscv/64bit-cpu.xml: Add register numbers.
	* features/riscv/64bit-fpu.c: Regenerate.
	* features/riscv/64bit-fpu.xml: Add register numbers.
2019-02-26 22:57:35 +02:00
..
arm
i386
riscv gdb/riscv: Use legacy register numbers in default target description 2019-02-26 22:57:35 +02:00
rs6000
sparc
aarch64-core.c
aarch64-core.xml
aarch64-fpu.c
aarch64-fpu.xml
aarch64-sve.c
aarch64.xml
arc-arcompact.c
arc-arcompact.xml
arc-v2.c
arc-v2.xml
btrace-conf.dtd
btrace.dtd
feature_to_c.sh
gdb-target.dtd
gdbserver-regs.xsl
library-list-aix.dtd
library-list-svr4.dtd
library-list.dtd
m68k-core.xml
Makefile
microblaze-core.xml
microblaze-stack-protect.xml
microblaze-with-stack-protect.c
microblaze-with-stack-protect.xml
microblaze.c
microblaze.xml
mips64-cp0.xml
mips64-cpu.xml
mips64-dsp-linux.c
mips64-dsp-linux.xml
mips64-dsp.xml
mips64-fpu.xml
mips64-linux.c
mips64-linux.xml
mips-cp0.xml
mips-cpu.xml
mips-dsp-linux.c
mips-dsp-linux.xml
mips-dsp.xml
mips-fpu.xml
mips-linux.c
mips-linux.xml
nds32-core.xml
nds32-fpu.xml
nds32-system.xml
nds32.c
nds32.xml
nios2-cpu.xml
nios2-linux.xml
nios2.c
nios2.xml
number-regs.xsl
or1k-core.xml
or1k.c
or1k.xml
osdata.dtd
s390-acr.xml
s390-core32.xml
s390-core64.xml
s390-fpr.xml
s390-gs-linux64.c
s390-gs-linux64.xml
s390-gs.xml
s390-gsbc.xml
s390-linux32.c
s390-linux32.xml
s390-linux32v1.c
s390-linux32v1.xml
s390-linux32v2.c
s390-linux32v2.xml
s390-linux64.c
s390-linux64.xml
s390-linux64v1.c
s390-linux64v1.xml
s390-linux64v2.c
s390-linux64v2.xml
s390-tdb.xml
s390-te-linux64.c
s390-te-linux64.xml
s390-tevx-linux64.c
s390-tevx-linux64.xml
s390-vx-linux64.c
s390-vx-linux64.xml
s390-vx.xml
s390x-core64.xml
s390x-gs-linux64.c
s390x-gs-linux64.xml
s390x-linux64.c
s390x-linux64.xml
s390x-linux64v1.c
s390x-linux64v1.xml
s390x-linux64v2.c
s390x-linux64v2.xml
s390x-te-linux64.c
s390x-te-linux64.xml
s390x-tevx-linux64.c
s390x-tevx-linux64.xml
s390x-vx-linux64.c
s390x-vx-linux64.xml
sort-regs.xsl
threads.dtd
tic6x-c6xp.c
tic6x-c6xp.xml
tic6x-c62x-linux.xml
tic6x-c64x-linux.xml
tic6x-c64xp-linux.xml
tic6x-core.c
tic6x-core.xml
tic6x-gp.c
tic6x-gp.xml
traceframe-info.dtd
xinclude.dtd