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25499ac7ee
Add MIPS16e2 ASE support as per the architecture specification[1], including in particular: 1. A new ELF ASE flag to mark MIPS16e2 binaries. 2. MIPS16e2 instruction assembly support, including a relaxation update to use LUI rather than an LI/SLL instruction pair for loading the high part of 32-bit addresses. 3. MIPS16e2 instruction disassembly support, including updated rules for extended forms of instructions that are now subdecoded and therefore do not alias to the original MIPS16 ISA revision instructions even for encodings that are not valid in the MIPS16e2 instruction set. Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and `.module' pseudo-ops. Control the availability of the MT ASE subset of the MIPS16e2 instruction set with a combination of these controls and the preexisting MT ASE controls. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific Extension Technical Reference Manual", Imagination Technologies Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016 include/ * elf/mips.h (AFL_ASE_MIPS16E2): New macro. (AFL_ASE_MASK): Adjust accordingly. * opcode/mips.h: Document new operand codes defined. (mips_operand_type): Add OP_REG28 enum value. (INSN2_SHORT_ONLY): Update description. (ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros. bfd/ * elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. (print_insn_arg) <OP_REG28>: Add handler. (validate_insn_args) <OP_REG28>: Handle. (print_mips16_insn_arg): Handle MIPS16 instructions that require 32-bit encoding and 9-bit immediates. (print_insn_mips16): Handle MIPS16 instructions that require 32-bit encoding and MFC0/MTC0 operand decoding. * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. (RD_C0, WR_C0, E2, E2MT): New macros. (mips16_opcodes): Add entries for MIPS16e2 instructions: GP-relative "addiu" and its "addu" spelling, "andi", "cache", "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" instructions, "swl", "swr", "sync" and its "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, "xori", "dmt", "dvpe", "emt" and "evpe". Add split regular/extended entries for original MIPS16 ISA revision instructions whose extended forms are subdecoded in the MIPS16e2 ISA revision: "li", "sll" and "srl". binutils/ * readelf.c (print_mips_ases): Handle MIPS16e2 ASE. * NEWS: Mention MIPS16e2 ASE support. gas/ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag. (RELAX_MIPS16_E2): New macro. (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO) (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT) (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT) (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED) (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED) (RELAX_MIPS16_MARK_ALWAYS_EXTENDED) (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO) (RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits. (mips16_immed_extend): New prototype. (options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum values. (md_longopts): Add "mmips16e2" and "mno-mips16e2" options. (mips_ases): Add "mips16e2" entry. (mips_set_ase): Handle MIPS16e2 ASE. (insn_insert_operand): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (is_opcode_valid_16): Pass enabled ASE bitmask on to `opcode_is_member'. (validate_mips_insn): Explicitly handle immediates with MIPS16 instructions that require 32-bit encoding. (operand_reg_mask) <OP_REG28>: Add handler. (match_reg28_operand): New function. (match_operand) <OP_REG28>: Add handler. (append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE. (match_mips16_insn): Handle MIPS16 instructions that require 32-bit encoding and `V' and `u' operand codes. (mips16_ip): Allow any characters except from `.' in opcodes. (mips16_immed_extend): Handle 9-bit immediates. Do not shuffle immediates whose width is not one of these listed. (md_estimate_size_before_relax): Handle MIPS16e2 relaxation. (mips_relax_frag): Likewise. (md_convert_frag): Likewise. (mips_convert_ase_flags): Handle MIPS16e2 ASE. * doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and `-mno-mips16e2' options. (-mmips16e2, -mno-mips16e2): New options. * doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and `-mno-mips16e2' options. (MIPS ASE Instruction Generation Overrides): Add `.set mips16e2' and `.set nomips16e2'. |
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aarch64.h | ||
alpha.h | ||
arc-reloc.def | ||
arc.h | ||
arm.h | ||
avr.h | ||
bfin.h | ||
ChangeLog-0415 | ||
ChangeLog-9103 | ||
common.h | ||
cr16.h | ||
cr16c.h | ||
cris.h | ||
crx.h | ||
d10v.h | ||
d30v.h | ||
dlx.h | ||
dwarf.h | ||
epiphany.h | ||
external.h | ||
fr30.h | ||
frv.h | ||
ft32.h | ||
h8.h | ||
hppa.h | ||
i370.h | ||
i386.h | ||
i860.h | ||
i960.h | ||
ia64.h | ||
internal.h | ||
ip2k.h | ||
iq2000.h | ||
lm32.h | ||
m32c.h | ||
m32r.h | ||
m68hc11.h | ||
m68k.h | ||
mcore.h | ||
mep.h | ||
metag.h | ||
microblaze.h | ||
mips.h | ||
mmix.h | ||
mn10200.h | ||
mn10300.h | ||
moxie.h | ||
msp430.h | ||
mt.h | ||
nds32.h | ||
nios2.h | ||
or1k.h | ||
pj.h | ||
ppc64.h | ||
ppc.h | ||
pru.h | ||
reloc-macros.h | ||
riscv.h | ||
rl78.h | ||
rx.h | ||
s390.h | ||
score.h | ||
sh.h | ||
sparc.h | ||
spu.h | ||
tic6x-attrs.h | ||
tic6x.h | ||
tilegx.h | ||
tilepro.h | ||
v850.h | ||
vax.h | ||
visium.h | ||
vxworks.h | ||
wasm32.h | ||
x86-64.h | ||
xc16x.h | ||
xgate.h | ||
xstormy16.h | ||
xtensa.h |