binutils-gdb/sim/example-synacor
Andrew Burgess 1d506c26d9 Update copyright year range in header of all files managed by GDB
This commit is the result of the following actions:

  - Running gdb/copyright.py to update all of the copyright headers to
    include 2024,

  - Manually updating a few files the copyright.py script told me to
    update, these files had copyright headers embedded within the
    file,

  - Regenerating gdbsupport/Makefile.in to refresh it's copyright
    date,

  - Using grep to find other files that still mentioned 2023.  If
    these files were updated last year from 2022 to 2023 then I've
    updated them this year to 2024.

I'm sure I've probably missed some dates.  Feel free to fix them up as
you spot them.
2024-01-12 15:49:57 +00:00
..
ChangeLog-2021
example-synacor-sim.h
interp.c
local.mk
README
README.arch-spec
sim-main.c
sim-main.h

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.