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78933a4ad9
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
107 lines
4.2 KiB
C
107 lines
4.2 KiB
C
/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
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Copyright (C) 2012-2021 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_ASM_H
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#define OPCODES_AARCH64_ASM_H
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#include "aarch64-opc.h"
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/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
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given LSL, return UBFM. */
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const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand inserter. */
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bool aarch64_insert_operand (const aarch64_operand *,
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const aarch64_opnd_info *, aarch64_insn *,
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const aarch64_inst *, aarch64_operand_error *);
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/* Operand inserters. */
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#define AARCH64_DECL_OPD_INSERTER(x) \
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bool aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
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aarch64_insn *, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_INSERTER (ins_none);
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AARCH64_DECL_OPD_INSERTER (ins_regno);
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AARCH64_DECL_OPD_INSERTER (ins_reglane);
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AARCH64_DECL_OPD_INSERTER (ins_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
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AARCH64_DECL_OPD_INSERTER (ins_imm);
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AARCH64_DECL_OPD_INSERTER (ins_imm_half);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
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AARCH64_DECL_OPD_INSERTER (ins_fpimm);
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AARCH64_DECL_OPD_INSERTER (ins_fbits);
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AARCH64_DECL_OPD_INSERTER (ins_aimm);
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AARCH64_DECL_OPD_INSERTER (ins_limm);
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AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
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AARCH64_DECL_OPD_INSERTER (ins_ft);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
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AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
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AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
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AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
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AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
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AARCH64_DECL_OPD_INSERTER (ins_cond);
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AARCH64_DECL_OPD_INSERTER (ins_sysreg);
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AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
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AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
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AARCH64_DECL_OPD_INSERTER (ins_barrier);
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AARCH64_DECL_OPD_INSERTER (ins_barrier_dsb_nxs);
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AARCH64_DECL_OPD_INSERTER (ins_hint);
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AARCH64_DECL_OPD_INSERTER (ins_prfop);
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AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
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AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
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AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
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AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
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AARCH64_DECL_OPD_INSERTER (ins_sve_index);
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AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
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AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
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AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
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AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
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AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
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AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
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AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
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#undef AARCH64_DECL_OPD_INSERTER
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#endif /* OPCODES_AARCH64_ASM_H */
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