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87ad46af87
This patch fixed those failures on elf configuration by:
* Improve the ILP32 target selector "aarch64_choose_ilp32_emul",
makes it more robust. Target triples copied from configure.tgt
* Updated emit-relocs-86/-overflow.d to use aarch64_choose_ilp32_emul
which is following what have done with emit-relocs-28.
* Those instruction encoding mismatch is because those encoding
contains pc-relative address. As for elf, we may have different
start address. relaxed encodind check, especially for
aarch64-farcall-b/bl-plt, as the main purpose of those check are
ELF text/data layout, we just want to make sure veneer to plt stub
is generated.
2015-08-12 Jiong Wang <jiong.wang@arm.com>
ld/testsuite/
* ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all
four triple shapes: aarch64-*-linux*, aarch64-*-elf,
aarch64_be-*-linux*, aarch64_be-*-elf.
* ld-aarch64/emit-relocs-86.d: Use aarch64_choose_ilp32_emul.
* ld-aarch64/emit-relocs-86-overflow.d: Likewise.
* ld-aarch64/ld-aarch64/farcall-b-plt.d: Relax instrucion encoding
check when they reflect address.
* ld-aarch64/ld-aarch64/farcall-bl-plt.d: Likewise.
39 lines
715 B
Makefile
39 lines
715 B
Makefile
#name: aarch64-farcall-bl-plt
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#source: farcall-bl-plt.s
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#as:
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#ld: -shared
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#objdump: -dr
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#...
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Disassembly of section .plt:
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.* <foo@plt.*>:
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.*: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
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.*: .* adrp x16, .* <__foo_veneer\+.*>
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.*: .* ldr x17, \[x16,#.*\]
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.*: .* add x16, x16, #.*
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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.* <foo@plt>:
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.*: .* adrp x16, .* <__foo_veneer\+.*>
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.*: .* ldr x17, \[x16,#.*\]
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.*: .* add x16, x16, #.*
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.*: d61f0220 br x17
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Disassembly of section .text:
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.* <_start>:
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...
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.*: .* bl .* <__foo_veneer>
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.*: d65f03c0 ret
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.*: .* b .* <__foo_veneer\+.*>
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.* <__foo_veneer>:
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.*: .* adrp x16, 0 <foo@plt.*>
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.*: .* add x16, x16, #.*
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.*: d61f0200 br x16
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...
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