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120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/* Copyright (C) 2009-2020 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef NAT_MIPS_LINUX_WATCH_H
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#define NAT_MIPS_LINUX_WATCH_H
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#include <asm/ptrace.h>
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#include "gdbsupport/break-common.h"
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#define MAX_DEBUG_REGISTER 8
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/* If macro PTRACE_GET_WATCH_REGS is not defined, kernel header doesn't
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have hardware watchpoint-related structures. Define them below. */
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#ifndef PTRACE_GET_WATCH_REGS
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# define PTRACE_GET_WATCH_REGS 0xd0
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# define PTRACE_SET_WATCH_REGS 0xd1
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enum pt_watch_style {
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pt_watch_style_mips32,
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pt_watch_style_mips64
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};
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/* A value of zero in a watchlo indicates that it is available. */
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struct mips32_watch_regs
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{
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uint32_t watchlo[MAX_DEBUG_REGISTER];
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/* Lower 16 bits of watchhi. */
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uint16_t watchhi[MAX_DEBUG_REGISTER];
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/* Valid mask and I R W bits.
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* bit 0 -- 1 if W bit is usable.
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* bit 1 -- 1 if R bit is usable.
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* bit 2 -- 1 if I bit is usable.
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* bits 3 - 11 -- Valid watchhi mask bits.
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*/
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uint16_t watch_masks[MAX_DEBUG_REGISTER];
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/* The number of valid watch register pairs. */
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uint32_t num_valid;
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/* There is confusion across gcc versions about structure alignment,
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so we force 8 byte alignment for these structures so they match
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the kernel even if it was build with a different gcc version. */
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} __attribute__ ((aligned (8)));
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struct mips64_watch_regs
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{
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uint64_t watchlo[MAX_DEBUG_REGISTER];
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uint16_t watchhi[MAX_DEBUG_REGISTER];
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uint16_t watch_masks[MAX_DEBUG_REGISTER];
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uint32_t num_valid;
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} __attribute__ ((aligned (8)));
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struct pt_watch_regs
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{
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enum pt_watch_style style;
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union
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{
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struct mips32_watch_regs mips32;
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struct mips64_watch_regs mips64;
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};
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};
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#endif /* !PTRACE_GET_WATCH_REGS */
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#define W_BIT 0
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#define R_BIT 1
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#define I_BIT 2
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#define W_MASK (1 << W_BIT)
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#define R_MASK (1 << R_BIT)
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#define I_MASK (1 << I_BIT)
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#define IRW_MASK (I_MASK | R_MASK | W_MASK)
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/* We keep list of all watchpoints we should install and calculate the
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watch register values each time the list changes. This allows for
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easy sharing of watch registers for more than one watchpoint. */
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struct mips_watchpoint
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{
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CORE_ADDR addr;
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int len;
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enum target_hw_bp_type type;
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struct mips_watchpoint *next;
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};
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uint32_t mips_linux_watch_get_num_valid (struct pt_watch_regs *regs);
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uint32_t mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n);
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CORE_ADDR mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n);
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void mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n,
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CORE_ADDR value);
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uint32_t mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n);
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void mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n,
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uint16_t value);
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int mips_linux_watch_try_one_watch (struct pt_watch_regs *regs,
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CORE_ADDR addr, int len, uint32_t irw);
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void mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches,
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struct pt_watch_regs *regs);
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uint32_t mips_linux_watch_type_to_irw (enum target_hw_bp_type type);
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int mips_linux_read_watch_registers (long lwpid,
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struct pt_watch_regs *watch_readback,
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int *watch_readback_valid, int force);
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#endif /* NAT_MIPS_LINUX_WATCH_H */
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