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cc917fd93d
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
345 lines
13 KiB
C
345 lines
13 KiB
C
/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
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Copyright (C) 2011-2017 Free Software Foundation, Inc.
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Contributed by Andrew Waterman
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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3, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef _RISCV_H_
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#define _RISCV_H_
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#include "riscv-opc.h"
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#include <stdlib.h>
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#include <stdint.h>
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typedef uint64_t insn_t;
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static inline unsigned int riscv_insn_length (insn_t insn)
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{
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if ((insn & 0x3) != 0x3) /* RVC. */
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return 2;
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if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
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return 4;
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if ((insn & 0x3f) == 0x1f) /* 48-bit extensions. */
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return 6;
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if ((insn & 0x7f) == 0x3f) /* 64-bit extensions. */
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return 8;
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/* Longer instructions not supported at the moment. */
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return 2;
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}
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static const char * const riscv_rm[8] =
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{
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"rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
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};
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static const char * const riscv_pred_succ[16] =
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{
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0, "w", "r", "rw", "o", "ow", "or", "orw",
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"i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
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};
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#define RVC_JUMP_BITS 11
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#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RVC_BRANCH_BITS 8
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#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define EXTRACT_ITYPE_IMM(x) \
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(RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_STYPE_IMM(x) \
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(RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_SBTYPE_IMM(x) \
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((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_UTYPE_IMM(x) \
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((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
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#define EXTRACT_UJTYPE_IMM(x) \
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((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
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#define EXTRACT_RVC_IMM(x) \
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(RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
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#define EXTRACT_RVC_LUI_IMM(x) \
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(EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
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#define EXTRACT_RVC_SIMM3(x) \
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(RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
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#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
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#define EXTRACT_RVC_ADDI16SP_IMM(x) \
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((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
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#define EXTRACT_RVC_LW_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
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#define EXTRACT_RVC_LD_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
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#define EXTRACT_RVC_LWSP_IMM(x) \
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((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
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#define EXTRACT_RVC_LDSP_IMM(x) \
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((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
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#define EXTRACT_RVC_SWSP_IMM(x) \
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((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
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#define EXTRACT_RVC_SDSP_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
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#define EXTRACT_RVC_B_IMM(x) \
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((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
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#define EXTRACT_RVC_J_IMM(x) \
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((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
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#define ENCODE_ITYPE_IMM(x) \
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(RV_X(x, 0, 12) << 20)
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#define ENCODE_STYPE_IMM(x) \
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((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
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#define ENCODE_SBTYPE_IMM(x) \
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((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
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#define ENCODE_UTYPE_IMM(x) \
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(RV_X(x, 12, 20) << 12)
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#define ENCODE_UJTYPE_IMM(x) \
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((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
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#define ENCODE_RVC_IMM(x) \
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((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
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#define ENCODE_RVC_LUI_IMM(x) \
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ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
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#define ENCODE_RVC_SIMM3(x) \
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(RV_X(x, 0, 3) << 10)
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#define ENCODE_RVC_ADDI4SPN_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
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#define ENCODE_RVC_ADDI16SP_IMM(x) \
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((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
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#define ENCODE_RVC_LW_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
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#define ENCODE_RVC_LD_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
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#define ENCODE_RVC_LWSP_IMM(x) \
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((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
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#define ENCODE_RVC_LDSP_IMM(x) \
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((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
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#define ENCODE_RVC_SWSP_IMM(x) \
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((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
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#define ENCODE_RVC_SDSP_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
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#define ENCODE_RVC_B_IMM(x) \
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((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
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#define ENCODE_RVC_J_IMM(x) \
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((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
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#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
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#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
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#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
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#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
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#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
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#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
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#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
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#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
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#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
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#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
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#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
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#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
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#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
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#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
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#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
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#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
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#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
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#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
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#define RISCV_RTYPE(insn, rd, rs1, rs2) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
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#define RISCV_ITYPE(insn, rd, rs1, imm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
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#define RISCV_STYPE(insn, rs1, rs2, imm) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
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#define RISCV_SBTYPE(insn, rs1, rs2, target) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
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#define RISCV_UTYPE(insn, rd, bigimm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
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#define RISCV_UJTYPE(insn, rd, target) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
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#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
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#define RVC_NOP MATCH_C_ADDI
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#define RISCV_CONST_HIGH_PART(VALUE) \
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(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
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#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
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#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
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#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
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#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
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#define RISCV_JUMP_ALIGN_BITS 1
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#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
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#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RISCV_IMM_BITS 12
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#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
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#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
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#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
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#define RISCV_RVC_IMM_REACH (1LL << 6)
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#define RISCV_BRANCH_BITS RISCV_IMM_BITS
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#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
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#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
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#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
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/* RV fields. */
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#define OP_MASK_OP 0x7f
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#define OP_SH_OP 0
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#define OP_MASK_RS2 0x1f
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#define OP_SH_RS2 20
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#define OP_MASK_RS1 0x1f
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#define OP_SH_RS1 15
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#define OP_MASK_RS3 0x1f
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#define OP_SH_RS3 27
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#define OP_MASK_RD 0x1f
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#define OP_SH_RD 7
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#define OP_MASK_SHAMT 0x3f
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#define OP_SH_SHAMT 20
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#define OP_MASK_SHAMTW 0x1f
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#define OP_SH_SHAMTW 20
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#define OP_MASK_RM 0x7
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#define OP_SH_RM 12
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#define OP_MASK_PRED 0xf
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#define OP_SH_PRED 24
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#define OP_MASK_SUCC 0xf
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#define OP_SH_SUCC 20
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#define OP_MASK_AQ 0x1
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#define OP_SH_AQ 26
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#define OP_MASK_RL 0x1
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#define OP_SH_RL 25
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#define OP_MASK_CUSTOM_IMM 0x7f
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#define OP_SH_CUSTOM_IMM 25
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#define OP_MASK_CSR 0xfff
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#define OP_SH_CSR 20
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/* RVC fields. */
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#define OP_MASK_CRS2 0x1f
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#define OP_SH_CRS2 2
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#define OP_MASK_CRS1S 0x7
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#define OP_SH_CRS1S 7
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#define OP_MASK_CRS2S 0x7
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#define OP_SH_CRS2S 2
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/* ABI names for selected x-registers. */
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#define X_RA 1
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#define X_SP 2
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#define X_GP 3
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#define X_TP 4
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#define X_T0 5
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#define X_T1 6
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#define X_T2 7
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#define X_T3 28
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#define NGPR 32
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#define NFPR 32
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/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
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VALUE << SHIFT. VALUE is evaluated exactly once. */
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#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
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(STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
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| ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
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/* Extract bits MASK << SHIFT from STRUCT and shift them right
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SHIFT places. */
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#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
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(((STRUCT) >> (SHIFT)) & (MASK))
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/* Extract the operand given by FIELD from integer INSN. */
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#define EXTRACT_OPERAND(FIELD, INSN) \
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EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
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/* This structure holds information for a particular instruction. */
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struct riscv_opcode
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{
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/* The name of the instruction. */
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const char *name;
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/* The ISA subset name (I, M, A, F, D, Xextension). */
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const char *subset;
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/* A string describing the arguments for this instruction. */
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const char *args;
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/* The basic opcode for the instruction. When assembling, this
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opcode is modified by the arguments to produce the actual opcode
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that is used. If pinfo is INSN_MACRO, then this is 0. */
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insn_t match;
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/* If pinfo is not INSN_MACRO, then this is a bit mask for the
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relevant portions of the opcode when disassembling. If the
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actual opcode anded with the match field equals the opcode field,
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then we have found the correct instruction. If pinfo is
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INSN_MACRO, then this field is the macro identifier. */
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insn_t mask;
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/* A function to determine if a word corresponds to this instruction.
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Usually, this computes ((word & mask) == match). */
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int (*match_func) (const struct riscv_opcode *op, insn_t word);
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/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
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of bits describing the instruction, notably any relevant hazard
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information. */
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unsigned long pinfo;
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};
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/* Instruction is a simple alias (e.g. "mv" for "addi"). */
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#define INSN_ALIAS 0x00000001
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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/* This is a list of macro expanded instructions.
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_I appended means immediate
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_A appended means address
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_AB appended means address with base register
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_D appended means 64 bit floating point constant
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_S appended means 32 bit floating point constant. */
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enum
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{
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M_LA,
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M_LLA,
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M_LA_TLS_GD,
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M_LA_TLS_IE,
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M_LB,
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M_LBU,
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M_LH,
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M_LHU,
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M_LW,
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M_LWU,
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M_LD,
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|
M_SB,
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|
M_SH,
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M_SW,
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|
M_SD,
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|
M_FLW,
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M_FLD,
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|
M_FLQ,
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|
M_FSW,
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M_FSD,
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|
M_FSQ,
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|
M_CALL,
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|
M_J,
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|
M_LI,
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|
M_NUM_MACROS
|
|
};
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|
|
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extern const char * const riscv_gpr_names_numeric[NGPR];
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extern const char * const riscv_gpr_names_abi[NGPR];
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extern const char * const riscv_fpr_names_numeric[NFPR];
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extern const char * const riscv_fpr_names_abi[NFPR];
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|
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extern const struct riscv_opcode riscv_opcodes[];
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#endif /* _RISCV_H_ */
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