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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
129 lines
3.8 KiB
Plaintext
129 lines
3.8 KiB
Plaintext
# frv testcase for msubaccs $ACC40Si,$ACC40Sk
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# mach: all
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.include "../testutils.inc"
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start
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.global msubaccs
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msubaccs:
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set_accg_immed 0,accg0
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set_acc_immed 0x00000000,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0x00000000,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg3
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test_acc_limmed 0x0000,0x0000,acc3
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set_accg_immed 0,accg0
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set_acc_immed 0xdead0000,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0x0000beef,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg3
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test_acc_limmed 0xdeac,0x4111,acc3
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set_accg_immed 0,accg0
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set_acc_immed 0x0000dead,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0xbeef0000,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0xff,accg3
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test_acc_limmed 0x4111,0xdead,acc3
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set_accg_immed 0,accg0
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set_acc_immed 0x12345678,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0x11111111,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg3
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test_acc_limmed 0x0123,0x4567,acc3
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set_accg_immed 0,accg0
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set_acc_immed 0x12345678,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0xffffffff,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0xff,accg3
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test_acc_limmed 0x1234,0x5679,acc3
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set_accg_immed 0,accg0
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set_acc_immed 0x12345678,acc0
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set_accg_immed 0xff,accg1
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set_acc_immed 0xffffffff,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set
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test_accg_immed 0,accg3
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test_acc_limmed 0x1234,0x5679,acc3
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set_spr_immed 0,msr0
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set_accg_immed 0x7f,accg0
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set_acc_immed 0xfffffffe,acc0
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set_accg_immed 0xff,accg1
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set_acc_immed 0xfffffffe,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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test_accg_immed 0x7f,accg3
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test_acc_limmed 0xffff,0xffff,acc3
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set_spr_immed 0,msr0
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set_accg_immed 0x80,accg0
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set_acc_immed 0x00000001,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0x00000002,acc1
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msubaccs acc0,acc3
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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test_accg_immed 0x80,accg3
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test_acc_limmed 0x0000,0x0000,acc3
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set_spr_immed 0,msr0
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set_accg_immed 0,accg0
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set_acc_immed 0x00000001,acc0
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set_accg_immed 0,accg1
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set_acc_immed 0x00000001,acc1
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set_accg_immed 0,accg4
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set_acc_immed 0x00000001,acc4
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set_accg_immed 0x80,accg5
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set_acc_immed 0x00000000,acc5
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msubaccs.p acc0,acc1
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msubaccs acc4,acc5
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test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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test_accg_immed 0,accg1
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test_acc_limmed 0x0000,0x0000,acc1
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test_accg_immed 0x7f,accg5
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test_acc_limmed 0xffff,0xffff,acc5
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pass
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