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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
169 lines
2.9 KiB
ArmAsm
169 lines
2.9 KiB
ArmAsm
//Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
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// Spec Reference: c_dspldst ld_drhi_i
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# mach: bfin
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.include "testutils.inc"
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start
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// set all regs
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INIT_R_REGS 0;
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loadsym i0, DATA_ADDR_3;
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loadsym i1, DATA_ADDR_4;
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loadsym i2, DATA_ADDR_5;
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loadsym i3, DATA_ADDR_6;
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// Load upper half of Dregs
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R0.H = W [ I0 ];
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R1.H = W [ I1 ];
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R2.H = W [ I2 ];
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R3.H = W [ I3 ];
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R4.H = W [ I0 ];
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R5.H = W [ I1 ];
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R6.H = W [ I2 ];
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R7.H = W [ I3 ];
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CHECKREG r0, 0x02030000;
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CHECKREG r1, 0x22230000;
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CHECKREG r2, 0x42430000;
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CHECKREG r3, 0x62630000;
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CHECKREG r4, 0x02030000;
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CHECKREG r5, 0x22230000;
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CHECKREG r6, 0x42430000;
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CHECKREG r7, 0x62630000;
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R1.H = W [ I0 ];
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R2.H = W [ I1 ];
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R3.H = W [ I2 ];
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R4.H = W [ I3 ];
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R5.H = W [ I0 ];
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R6.H = W [ I1 ];
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R7.H = W [ I2 ];
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R0.H = W [ I3 ];
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CHECKREG r0, 0x62630000;
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CHECKREG r1, 0x02030000;
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CHECKREG r2, 0x22230000;
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CHECKREG r3, 0x42430000;
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CHECKREG r4, 0x62630000;
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CHECKREG r5, 0x02030000;
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CHECKREG r6, 0x22230000;
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CHECKREG r7, 0x42430000;
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R2.H = W [ I0 ];
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R3.H = W [ I1 ];
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R4.H = W [ I2 ];
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R5.H = W [ I3 ];
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R6.H = W [ I0 ];
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R7.H = W [ I1 ];
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R0.H = W [ I2 ];
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R1.H = W [ I3 ];
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CHECKREG r0, 0x42430000;
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CHECKREG r1, 0x62630000;
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CHECKREG r2, 0x02030000;
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CHECKREG r3, 0x22230000;
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CHECKREG r4, 0x42430000;
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CHECKREG r5, 0x62630000;
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CHECKREG r6, 0x02030000;
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CHECKREG r7, 0x22230000;
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R3.H = W [ I0 ];
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R4.H = W [ I1 ];
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R5.H = W [ I2 ];
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R6.H = W [ I3 ];
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R7.H = W [ I0 ];
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R0.H = W [ I1 ];
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R1.H = W [ I2 ];
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R2.H = W [ I3 ];
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CHECKREG r0, 0x22230000;
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CHECKREG r1, 0x42430000;
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CHECKREG r2, 0x62630000;
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CHECKREG r3, 0x02030000;
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CHECKREG r4, 0x22230000;
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CHECKREG r5, 0x42430000;
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CHECKREG r6, 0x62630000;
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CHECKREG r7, 0x02030000;
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pass
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// Pre-load memory with known data
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// More data is defined than will actually be used
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.data
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DATA_ADDR_3:
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.dd 0x00010203
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.dd 0x04050607
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.dd 0x08090A0B
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.dd 0x0C0D0E0F
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.dd 0x10111213
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.dd 0x14151617
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.dd 0x18191A1B
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.dd 0x1C1D1E1F
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DATA_ADDR_4:
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.dd 0x20212223
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.dd 0x24252627
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.dd 0x28292A2B
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.dd 0x2C2D2E2F
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.dd 0x30313233
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.dd 0x34353637
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.dd 0x38393A3B
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.dd 0x3C3D3E3F
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DATA_ADDR_5:
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.dd 0x40414243
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.dd 0x44454647
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.dd 0x48494A4B
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.dd 0x4C4D4E4F
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.dd 0x50515253
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.dd 0x54555657
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.dd 0x58595A5B
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.dd 0x5C5D5E5F
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DATA_ADDR_6:
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.dd 0x60616263
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.dd 0x64656667
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.dd 0x68696A6B
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.dd 0x6C6D6E6F
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.dd 0x70717273
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.dd 0x74757677
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.dd 0x78797A7B
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.dd 0x7C7D7E7F
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DATA_ADDR_7:
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.dd 0x80818283
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.dd 0x84858687
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.dd 0x88898A8B
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.dd 0x8C8D8E8F
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.dd 0x90919293
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.dd 0x94959697
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.dd 0x98999A9B
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.dd 0x9C9D9E9F
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DATA_ADDR_8:
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.dd 0xA0A1A2A3
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.dd 0xA4A5A6A7
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.dd 0xA8A9AAAB
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.dd 0xACADAEAF
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.dd 0xB0B1B2B3
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.dd 0xB4B5B6B7
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.dd 0xB8B9BABB
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.dd 0xBCBDBEBF
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.dd 0xC0C1C2C3
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.dd 0xC4C5C6C7
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.dd 0xC8C9CACB
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.dd 0xCCCDCECF
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.dd 0xD0D1D2D3
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.dd 0xD4D5D6D7
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.dd 0xD8D9DADB
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.dd 0xDCDDDEDF
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.dd 0xE0E1E2E3
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.dd 0xE4E5E6E7
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.dd 0xE8E9EAEB
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.dd 0xECEDEEEF
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.dd 0xF0F1F2F3
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.dd 0xF4F5F6F7
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.dd 0xF8F9FAFB
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.dd 0xFCFDFEFF
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