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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
540 lines
8.6 KiB
ArmAsm
540 lines
8.6 KiB
ArmAsm
//Original:/testcases/core/c_ccflag_pr_imm3/c_ccflag_pr_imm3.dsp
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// Spec Reference: ccflag pr-imm3
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS 0;
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//imm32 p0, 0x00000001;
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imm32 p1, 0x00000001;
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imm32 p2, 0x00000002;
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imm32 p3, 0x00000003;
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imm32 p4, 0x00000001;
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imm32 p5, 0x00000002;
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imm32 sp, 0x00000003;
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imm32 fp, 0x00000003;
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R0 = 0;
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ASTAT = R0;
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// positive dreg EQUAL to positive imm3
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CC = P1 == 1;
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R0 = ASTAT;
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CC = P1 < 1;
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R1 = ASTAT;
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CC = P1 <= 1;
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R2 = ASTAT;
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CC = P2 == 2;
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R3 = ASTAT;
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CC = P2 < 2;
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R4 = ASTAT;
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CC = P2 <= 2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = P3 == 3;
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R0 = ASTAT;
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CC = P3 < 3;
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R1 = ASTAT;
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CC = P3 <= 3;
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R2 = ASTAT;
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CC = P4 == 1;
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R3 = ASTAT;
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CC = P4 < 1;
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R4 = ASTAT;
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CC = P4 <= 1;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = P5 == 2;
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R0 = ASTAT;
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CC = P5 < 2;
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R1 = ASTAT;
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CC = P5 <= 2;
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R2 = ASTAT;
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CC = SP == 3;
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R3 = ASTAT;
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CC = SP < 3;
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R4 = ASTAT;
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CC = SP <= 3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = FP == 3;
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R5 = ASTAT;
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CC = FP < 3;
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R6 = ASTAT;
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CC = FP <= 3;
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R7 = ASTAT;
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CHECKREG r5, 0x00000020;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000020;
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// positive dreg GREATER than positive imm3
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imm32 p1, 0x00000002;
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imm32 p2, 0x00000002;
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imm32 p3, 0x00000003;
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imm32 p4, 0x00000002;
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imm32 p5, 0x00000002;
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imm32 sp, 0x00000003;
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imm32 fp, 0x00000003;
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CC = P1 == 0;
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R0 = ASTAT;
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CC = P1 < 0;
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R1 = ASTAT;
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CC = P1 <= 0;
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R2 = ASTAT;
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CC = P2 == 1;
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R3 = ASTAT;
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CC = P2 < 1;
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R4 = ASTAT;
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CC = P2 <= 1;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P3 == 2;
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R0 = ASTAT;
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CC = P3 < 2;
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R1 = ASTAT;
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CC = P3 <= 2;
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R2 = ASTAT;
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CC = P4 == 0;
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R3 = ASTAT;
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CC = P4 < 0;
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R4 = ASTAT;
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CC = P4 <= 0;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P5 == 1;
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R0 = ASTAT;
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CC = P5 < 1;
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R1 = ASTAT;
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CC = P5 <= 1;
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R2 = ASTAT;
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CC = SP == 2;
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R3 = ASTAT;
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CC = SP < 2;
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R4 = ASTAT;
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CC = SP <= 2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = FP == 2;
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R5 = ASTAT;
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CC = FP < 2;
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R6 = ASTAT;
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CC = FP <= 2;
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R7 = ASTAT;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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// positive dreg LESS than positive imm3
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imm32 p1, 0x00000001;
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imm32 p2, 0x00000002;
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imm32 p3, 0x00000002;
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imm32 p4, 0x00000001;
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imm32 p5, 0x00000001;
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imm32 sp, 0x00000002;
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imm32 fp, 0x00000002;
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CC = P1 == 2;
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R0 = ASTAT;
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CC = P1 < 2;
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R1 = ASTAT;
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CC = P1 <= 2;
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R2 = ASTAT;
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CC = P2 == 3;
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R3 = ASTAT;
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CC = P2 < 3;
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R4 = ASTAT;
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CC = P2 <= 3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = P3 == 3;
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R0 = ASTAT;
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CC = P3 < 3;
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R1 = ASTAT;
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CC = P3 <= 3;
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R2 = ASTAT;
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CC = P4 == 3;
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R3 = ASTAT;
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CC = P4 < 3;
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R4 = ASTAT;
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CC = P4 <= 3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = P5 == 3;
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R0 = ASTAT;
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CC = P5 < 3;
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R1 = ASTAT;
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CC = P5 <= 3;
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R2 = ASTAT;
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CC = SP == 3;
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R3 = ASTAT;
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CC = SP < 3;
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R4 = ASTAT;
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CC = SP <= 3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = FP == 3;
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R5 = ASTAT;
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CC = FP < 3;
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R6 = ASTAT;
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CC = FP <= 3;
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R7 = ASTAT;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000020;
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CHECKREG r7, 0x00000020;
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// positive dreg GREATER than neg imm3
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CC = P1 == -1;
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R0 = ASTAT;
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CC = P1 < -1;
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R1 = ASTAT;
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CC = P1 <= -1;
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R2 = ASTAT;
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CC = P2 == -2;
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R3 = ASTAT;
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CC = P2 < -2;
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R4 = ASTAT;
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CC = P2 <= -2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P3 == -3;
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R0 = ASTAT;
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CC = P3 < -3;
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R1 = ASTAT;
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CC = P3 <= -3;
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R2 = ASTAT;
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CC = P4 == -4;
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R3 = ASTAT;
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CC = P4 < -4;
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R4 = ASTAT;
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CC = P4 <= -4;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P5 == -1;
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R0 = ASTAT;
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CC = P5 < -1;
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R1 = ASTAT;
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CC = P5 <= -1;
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R2 = ASTAT;
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CC = SP == -2;
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R3 = ASTAT;
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CC = SP < -2;
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R4 = ASTAT;
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CC = SP <= -2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = FP == -4;
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R5 = ASTAT;
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CC = FP < -4;
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R6 = ASTAT;
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CC = FP <= -4;
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R7 = ASTAT;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 p1, -1;
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imm32 p2, -2;
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imm32 p3, -3;
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imm32 p4, -4;
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imm32 p5, -1;
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imm32 sp, -2;
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imm32 fp, -3;
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// negative dreg equal negative imm3
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CC = P1 == -1;
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R0 = ASTAT;
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CC = P1 < -1;
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R1 = ASTAT;
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CC = P1 <= -1;
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R2 = ASTAT;
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CC = P2 == -2;
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R3 = ASTAT;
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CC = P2 < -2;
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R4 = ASTAT;
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CC = P2 <= -2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = P3 == -3;
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R0 = ASTAT;
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CC = P3 < -3;
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R1 = ASTAT;
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CC = P3 <= -3;
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R2 = ASTAT;
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CC = P4 == -4;
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R3 = ASTAT;
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CC = P4 < -4;
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R4 = ASTAT;
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CC = P4 <= -4;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = P5 == -1;
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R0 = ASTAT;
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CC = P5 < -1;
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R1 = ASTAT;
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CC = P5 <= -1;
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R2 = ASTAT;
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CC = SP == -2;
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R3 = ASTAT;
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CC = SP < -2;
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R4 = ASTAT;
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CC = SP <= -2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000020;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000020;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000020;
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CC = FP == -3;
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R5 = ASTAT;
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CC = FP < -3;
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R6 = ASTAT;
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CC = FP <= -3;
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R7 = ASTAT;
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CHECKREG r5, 0x00000020;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000020;
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// negative dreg GREATER neg imm3
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imm32 p1, -1;
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imm32 p2, -1;
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imm32 p3, -2;
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imm32 p4, -3;
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imm32 p5, -1;
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imm32 sp, -2;
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imm32 fp, -3;
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CC = P1 == -2;
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R0 = ASTAT;
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CC = P1 < -2;
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R1 = ASTAT;
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CC = P1 <= -2;
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R2 = ASTAT;
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CC = P2 == -3;
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R3 = ASTAT;
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CC = P2 < -3;
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R4 = ASTAT;
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CC = P2 <= -3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P3 == -4;
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R0 = ASTAT;
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CC = P3 < -4;
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R1 = ASTAT;
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CC = P3 <= -4;
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R2 = ASTAT;
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CC = P4 == -4;
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R3 = ASTAT;
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CC = P4 < -4;
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R4 = ASTAT;
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CC = P4 <= -4;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = P5 == -2;
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R0 = ASTAT;
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CC = P5 < -2;
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R1 = ASTAT;
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CC = P5 <= -2;
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R2 = ASTAT;
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CC = SP == -3;
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R3 = ASTAT;
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CC = SP < -3;
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R4 = ASTAT;
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CC = SP <= -3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CC = FP == -4;
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R5 = ASTAT;
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CC = FP < -4;
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R6 = ASTAT;
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CC = FP <= -4;
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R7 = ASTAT;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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// negative dreg LESS than neg imm3
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imm32 p1, -2;
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imm32 p2, -2;
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imm32 p3, -3;
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imm32 p4, -3;
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imm32 p5, -4;
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imm32 sp, -4;
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imm32 fp, -4;
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imm32 p4, -4;
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CC = P1 == -1;
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R0 = ASTAT;
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CC = P1 < -1;
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R1 = ASTAT;
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CC = P1 <= -1;
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R2 = ASTAT;
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CC = P2 == -1;
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R3 = ASTAT;
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CC = P2 < -1;
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R4 = ASTAT;
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CC = P2 <= -1;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = P3 == -2;
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R0 = ASTAT;
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CC = P3 < -2;
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R1 = ASTAT;
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CC = P3 <= -2;
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R2 = ASTAT;
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CC = P4 == -2;
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R3 = ASTAT;
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CC = P4 < -2;
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R4 = ASTAT;
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CC = P4 <= -2;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = P5 == -3;
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R0 = ASTAT;
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CC = P5 < -3;
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R1 = ASTAT;
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CC = P5 <= -3;
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R2 = ASTAT;
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CC = SP == -3;
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R3 = ASTAT;
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CC = SP < -3;
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R4 = ASTAT;
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CC = SP <= -3;
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R5 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000020;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000020;
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CHECKREG r5, 0x00000020;
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CC = FP == -3;
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R5 = ASTAT;
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CC = FP < -3;
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R6 = ASTAT;
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CC = FP <= -3;
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R7 = ASTAT;
|
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CHECKREG r5, 0x00000000;
|
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CHECKREG r6, 0x00000020;
|
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CHECKREG r7, 0x00000020;
|
|
|
|
|
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pass
|