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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
446 lines
7.9 KiB
ArmAsm
446 lines
7.9 KiB
ArmAsm
# Hitachi H8 testcase 'ldc'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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start
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.data
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.align 4
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stack:
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.if (sim_cpu == h8300)
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.fill 128, 2, 0
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.else
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.fill 128, 4, 0
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.endif
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stacktop:
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.text
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push_w:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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.if (sim_cpu == h8300)
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mov.w #stacktop, r7
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.else
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mov.l #stacktop, er7
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.endif
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push.w r0 ; a5a5 is negative
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test_neg_set
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test_carry_clear
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test_zero_clear
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test_ovf_clear
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push.w r1
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push.w r2
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push.w r3
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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mov @stacktop-2, r0
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test_gr_a5a5 0
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mov @stacktop-4, r0
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test_gr_a5a5 0
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mov @stacktop-6, r0
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test_gr_a5a5 0
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mov @stacktop-8, r0
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test_gr_a5a5 0
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mov.w #1, r1
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mov.w #2, r2
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mov.w #3, r3
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mov.w #4, r4
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push.w r1 ; #1 is non-negative, non-zero
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test_cc_clear
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push.w r2
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push.w r3
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push.w r4
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test_h_gr16 1 r1
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test_h_gr16 2 r2
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test_h_gr16 3 r3
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test_h_gr16 4 r4
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mov @stacktop-10, r0
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test_h_gr16 1 r0
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mov @stacktop-12, r0
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test_h_gr16 2 r0
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mov @stacktop-14, r0
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test_h_gr16 3 r0
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mov @stacktop-16, r0
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test_h_gr16 4 r0
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.if (sim_cpu == h8300)
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test_h_gr16 4 r0
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test_h_gr16 1 r1
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test_h_gr16 2 r2
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test_h_gr16 3 r3
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test_h_gr16 4 r4
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;;; test_h_gr16 stacktop-16 r7 ; FIXME
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.else
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test_h_gr32 0xa5a50004 er0
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test_h_gr32 0xa5a50001 er1
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test_h_gr32 0xa5a50002 er2
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test_h_gr32 0xa5a50003 er3
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test_h_gr32 0xa5a50004 er4
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test_h_gr32 stacktop-16 er7
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.endif
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test_gr_a5a5 5
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test_gr_a5a5 6
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pop_w:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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.if (sim_cpu == h8300)
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mov.w #stacktop-16, r7
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.else
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mov.l #stacktop-16, er7
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.endif
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pop.w r4
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pop.w r3
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pop.w r2
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pop.w r1 ; Should set all flags zero
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test_cc_clear
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test_h_gr16 1 r1
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test_h_gr16 2 r2
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test_h_gr16 3 r3
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test_h_gr16 4 r4
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pop.w r4
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pop.w r3
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pop.w r2
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pop.w r1 ; a5a5 is negative
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test_neg_set
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test_carry_clear
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test_zero_clear
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test_ovf_clear
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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.if (sim_cpu == h8300)
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;;; test_h_gr16 stacktop r7 ; FIXME
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.else
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test_h_gr32 stacktop er7
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.endif
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.if (sim_cpu) ; non-zero means not h8300
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push_l:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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mov.l #stacktop, er7
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push.l er0 ; a5a5 is negative
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test_neg_set
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test_carry_clear
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test_zero_clear
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test_ovf_clear
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push.l er1
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push.l er2
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push.l er3
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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mov @stacktop-4, er0
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test_gr_a5a5 0
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mov @stacktop-8, er0
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test_gr_a5a5 0
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mov @stacktop-12, er0
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test_gr_a5a5 0
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mov @stacktop-16, er0
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test_gr_a5a5 0
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mov #1, er1
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mov #2, er2
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mov #3, er3
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mov #4, er4
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push.l er1 ; #1 is non-negative, non-zero
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test_cc_clear
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push.l er2
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push.l er3
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push.l er4
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test_h_gr32 1 er1
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test_h_gr32 2 er2
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test_h_gr32 3 er3
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test_h_gr32 4 er4
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mov @stacktop-20, er0
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test_h_gr32 1 er0
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mov @stacktop-24, er0
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test_h_gr32 2 er0
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mov @stacktop-28, er0
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test_h_gr32 3 er0
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mov @stacktop-32, er0
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test_h_gr32 4 er0
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test_h_gr32 4 er0
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test_h_gr32 1 er1
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test_h_gr32 2 er2
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test_h_gr32 3 er3
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test_h_gr32 4 er4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 stacktop-32 er7
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pop_l:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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mov.l #stacktop-32, er7
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pop.l er4
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pop.l er3
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pop.l er2
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pop.l er1 ; Should set all flags zero
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test_cc_clear
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test_h_gr32 1 er1
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test_h_gr32 2 er2
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test_h_gr32 3 er3
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test_h_gr32 4 er4
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pop.l er4
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pop.l er3
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pop.l er2
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pop.l er1 ; a5a5 is negative
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test_neg_set
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test_carry_clear
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test_zero_clear
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test_ovf_clear
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_h_gr32 stacktop er7
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.endif
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;; Jump over subroutine
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jmp _bsr
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bsr_jsr_func:
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test_ccr 0 ; call should not affect ccr
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mov.w #0, r0
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mov.w #1, r1
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mov.w #2, r2
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mov.w #3, r3
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mov.w #4, r4
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mov.w #5, r5
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mov.w #6, r6
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rts
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_bsr: set_grs_a5a5
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.if (sim_cpu == h8300)
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mov.w #stacktop, r7
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.else
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mov.l #stacktop, er7
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.endif
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set_ccr_zero
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bsr bsr_jsr_func
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test_h_gr16 0 r0
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test_h_gr16 1 r1
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test_h_gr16 2 r2
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test_h_gr16 3 r3
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test_h_gr16 4 r4
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test_h_gr16 5 r5
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test_h_gr16 6 r6
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.if (sim_cpu == h8300)
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;;; test_h_gr16 stacktop, r7 ; FIXME
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.else
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test_h_gr32 stacktop, er7
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.endif
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_jsr: set_grs_a5a5
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.if (sim_cpu == h8300)
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mov.w #stacktop, r7
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.else
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mov.l #stacktop, er7
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.endif
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set_ccr_zero
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jsr bsr_jsr_func
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test_h_gr16 0 r0
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test_h_gr16 1 r1
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test_h_gr16 2 r2
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test_h_gr16 3 r3
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test_h_gr16 4 r4
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test_h_gr16 5 r5
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test_h_gr16 6 r6
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.if (sim_cpu == h8300)
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;;; test_h_gr16 stacktop, r7 ; FIXME
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.else
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test_h_gr32 stacktop, er7
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.endif
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.if (sim_cpu) ; not zero ie. not h8300
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_trapa:
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set_grs_a5a5
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mov.l #trap_handler, er7 ; trap vector
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mov.l er7, @0x2c
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mov.l #stacktop, er7
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set_ccr_zero
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trapa #3
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test_cc_clear ; ccr should be restored by rte
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test_h_gr16 0x10 r0
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test_h_gr16 0x11 r1
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test_h_gr16 0x12 r2
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test_h_gr16 0x13 r3
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test_h_gr16 0x14 r4
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test_h_gr16 0x15 r5
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test_h_gr16 0x16 r6
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test_h_gr32 stacktop er7
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.endif
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.if (sim_cpu == h8sx)
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_rtsl: ; Test rts/l insn.
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set_grs_a5a5
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mov #0,r0l
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mov #1,r1l
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mov #2,r2l
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mov #3,r3l
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mov #4,r4l
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mov #5,r5l
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mov #6,r6l
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mov #stacktop, er7
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jsr rtsl1_func
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test_h_gr32 0xa5a5a500 er0
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test_h_gr32 0xa5a5a501 er1
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test_h_gr32 0xa5a5a502 er2
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test_h_gr32 0xa5a5a503 er3
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test_h_gr32 0xa5a5a504 er4
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test_h_gr32 0xa5a5a505 er5
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test_h_gr32 0xa5a5a506 er6
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test_h_gr32 stacktop er7
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jsr rtsl2_func
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test_h_gr32 0xa5a5a500 er0
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test_h_gr32 0xa5a5a501 er1
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test_h_gr32 0xa5a5a502 er2
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test_h_gr32 0xa5a5a503 er3
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test_h_gr32 0xa5a5a504 er4
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test_h_gr32 0xa5a5a505 er5
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test_h_gr32 0xa5a5a506 er6
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test_h_gr32 stacktop er7
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jsr rtsl3_func
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test_h_gr32 0xa5a5a500 er0
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test_h_gr32 0xa5a5a501 er1
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test_h_gr32 0xa5a5a502 er2
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test_h_gr32 0xa5a5a503 er3
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test_h_gr32 0xa5a5a504 er4
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test_h_gr32 0xa5a5a505 er5
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test_h_gr32 0xa5a5a506 er6
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test_h_gr32 stacktop er7
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jsr rtsl4_func
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test_h_gr32 0xa5a5a500 er0
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test_h_gr32 0xa5a5a501 er1
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test_h_gr32 0xa5a5a502 er2
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test_h_gr32 0xa5a5a503 er3
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test_h_gr32 0xa5a5a504 er4
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test_h_gr32 0xa5a5a505 er5
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test_h_gr32 0xa5a5a506 er6
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test_h_gr32 stacktop er7
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.endif ; h8sx
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pass
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exit 0
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;; Handler for a software exception (trap).
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trap_handler:
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;; Test the 'i' interrupt mask flag.
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stc ccr, r0l
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test_h_gr8 0x80, r0l
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;; Change the registers (so we know we've been here)
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mov.w #0x10, r0
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mov.w #0x11, r1
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mov.w #0x12, r2
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mov.w #0x13, r3
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mov.w #0x14, r4
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mov.w #0x15, r5
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mov.w #0x16, r6
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;; Change the ccr (which will be restored by RTE)
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orc #0xff, ccr
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rte
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.if (sim_cpu == h8sx)
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;; Functions for testing rts/l
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rtsl1_func: ; Save and restore R0
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push.l er0
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;; Now modify it, and verify the modification.
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mov #0xfeedface, er0
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test_h_gr32 0xfeedface, er0
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;; Then use rts/l to restore them and return.
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rts/l er0
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rtsl2_func: ; Save and restore R5 and R6
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push.l er5
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push.l er6
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;; Now modify them, and verify the modification.
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mov #0xdeadbeef, er5
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mov #0xfeedface, er6
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test_h_gr32 0xdeadbeef, er5
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test_h_gr32 0xfeedface, er6
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;; Then use rts/l to restore them and return.
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rts/l (er5-er6)
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rtsl3_func: ; Save and restore R4, R5, and R6
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push.l er4
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push.l er5
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push.l er6
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;; Now modify them, and verify the modification.
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mov #0xdeafcafe, er4
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mov #0xdeadbeef, er5
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mov #0xfeedface, er6
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test_h_gr32 0xdeafcafe, er4
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test_h_gr32 0xdeadbeef, er5
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test_h_gr32 0xfeedface, er6
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;; Then use rts/l to restore them and return.
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rts/l (er4-er6)
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rtsl4_func: ; Save and restore R0 - R3
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push.l er0
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push.l er1
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push.l er2
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push.l er3
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;; Now modify them, and verify the modification.
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mov #0xdadacafe, er0
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mov #0xfeedbeef, er1
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mov #0xdeadface, er2
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mov #0xf00dd00d, er3
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test_h_gr32 0xdadacafe, er0
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test_h_gr32 0xfeedbeef, er1
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test_h_gr32 0xdeadface, er2
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test_h_gr32 0xf00dd00d, er3
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;; Then use rts/l to restore them and return.
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rts/l (er0-er3)
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.endif ; h8sx
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