mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
581 lines
11 KiB
ArmAsm
581 lines
11 KiB
ArmAsm
# Hitachi H8 testcase 'exts.w, extu.w'
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# mach(): h8300h h8300s h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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start
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.data
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.align 2
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pos: .word 0xff01
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neg: .word 0x0080
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.text
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exts_w_reg16_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w rn16
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mov.b #1, r0l
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exts.w r0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 0xa5a50001 er0 ; result of sign extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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exts_w_reg16_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w rn16
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mov.b #0xff, r0l
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exts.w r0
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 0xa5a5ffff er0 ; result of sign extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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extu_w_reg16_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w rn16
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mov.b #0xff, r0l
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extu.w r0
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 0xa5a500ff er0 ; result of zero extend
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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exts_w_ind_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern
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mov.l #pos, er1
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exts.w @er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 pos er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0001, @pos
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beq .Lswindp
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fail
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.Lswindp:
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mov.w #0xff01, @pos ; Restore initial value
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exts_w_ind_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern
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mov.l #neg, er1
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exts.w @er1
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0xff80, @neg
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beq .Lswindn
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fail
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.Lswindn:
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;; Note: leave the value as 0xff80, so that extu has work to do.
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extu_w_ind_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @ern
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mov.l #neg, er1
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extu.w @er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwindn
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fail
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.Luwindn:
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;; Note: leave the value as 0x0080, like it started out.
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exts_w_postinc_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern+
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mov.l #pos, er1
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exts.w @er1+
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0001, @pos
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beq .Lswpostincp
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fail
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.Lswpostincp:
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mov.w #0xff01, @pos ; Restore initial value
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exts_w_postinc_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern+
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mov.l #neg, er1
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exts.w @er1+
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 neg+2 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0xff80, @neg
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beq .Lswpostincn
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fail
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.Lswpostincn:
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;; Note: leave the value as 0xff80, so that extu has work to do.
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extu_w_postinc_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @ern+
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mov.l #neg, er1
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extu.w @er1+
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg+2 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwpostincn
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fail
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.Luwpostincn:
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;; Note: leave the value as 0x0080, like it started out.
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exts_w_postdec_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern-
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mov.l #pos, er1
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exts.w @er1-
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0001, @pos
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beq .Lswpostdecp
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fail
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.Lswpostdecp:
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mov.w #0xff01, @pos ; Restore initial value
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exts_w_postdec_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @ern-
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mov.l #neg, er1
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exts.w @er1-
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 neg-2 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0xff80, @neg
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beq .Lswpostdecn
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fail
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.Lswpostdecn:
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;; Note: leave the value as 0xff80, so that extu has work to do.
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extu_w_postdec_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @ern-
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mov.l #neg, er1
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extu.w @er1-
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg-2 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwpostdecn
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fail
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.Luwpostdecn:
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;; Note: leave the value as 0x0080, like it started out.
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exts_w_preinc_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @+ern
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mov.l #pos-2, er1
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exts.w @+er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 pos er1 ; er1 still contains target address plus 2
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0001, @pos
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beq .Lswpreincp
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fail
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.Lswpreincp:
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mov.w #0xff01, @pos ; Restore initial value
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exts_w_preinc_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @+ern
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mov.l #neg-2, er1
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exts.w @+er1
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0xff80, @neg
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beq .Lswpreincn
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fail
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.Lswpreincn:
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;; Note: leave the value as 0xff80, so that extu has work to do.
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extu_w_preinc_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @+ern
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mov.l #neg-2, er1
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extu.w @+er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwpreincn
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fail
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.Luwpreincn:
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;; Note: leave the value as 0x0080, like it started out.
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exts_w_predec_p:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @-ern
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mov.l #pos+2, er1
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exts.w @-er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 pos er1 ; er1 still contains target address plus 2
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0001, @pos
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beq .Lswpredecp
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fail
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.Lswpredecp:
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mov.w #0xff01, @pos ; Restore initial value
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exts_w_predec_n:
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set_grs_a5a5
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set_ccr_zero
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;; exts.w @-ern
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mov.l #neg+2, er1
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exts.w @-er1
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;; Test ccr H=0 N=1 Z=0 V=0 C=0
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test_neg_set
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test_zero_clear
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test_ovf_clear
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test_carry_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0xff80, @neg
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beq .Lswpredecn
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fail
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.Lswpredecn:
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;; Note: leave the value as 0xff80, so that extu has work to do.
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extu_w_predec_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @-ern
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mov.l #neg+2, er1
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extu.w @-er1
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwpredecn
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fail
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.Luwpredecn:
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;; Note: leave the value as 0x0080, like it started out.
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extu_w_disp2_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @(dd:2, ern)
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mov.l #neg-2, er1
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extu.w @(2:2, er1)
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg-2 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp.w #0x0080, @neg
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beq .Luwdisp2n
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fail
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.Luwdisp2n:
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;; Note: leave the value as 0x0080, like it started out.
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extu_w_disp16_n:
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set_grs_a5a5
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set_ccr_zero
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;; extu.w @(dd:16, ern)
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mov.l #neg-44, er1
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extu.w @(44:16, er1)
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;; Test ccr H=0 N=0 Z=0 V=0 C=0
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test_cc_clear
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test_h_gr32 neg-44 er1 ; er1 still contains target address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
cmp.w #0x0080, @neg
|
|
beq .Luwdisp16n
|
|
fail
|
|
.Luwdisp16n:
|
|
;; Note: leave the value as 0x0080, like it started out.
|
|
|
|
extu_w_disp32_n:
|
|
set_grs_a5a5
|
|
set_ccr_zero
|
|
;; extu.w @(dd:32, ern)
|
|
mov.l #neg+444, er1
|
|
extu.w @(-444:32, er1)
|
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
|
test_cc_clear
|
|
|
|
test_h_gr32 neg+444 er1 ; er1 still contains target address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
cmp.w #0x0080, @neg
|
|
beq .Luwdisp32n
|
|
fail
|
|
.Luwdisp32n:
|
|
;; Note: leave the value as 0x0080, like it started out.
|
|
|
|
extu_w_abs16_n:
|
|
set_grs_a5a5
|
|
set_ccr_zero
|
|
;; extu.w @aa:16
|
|
extu.w @neg:16
|
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
|
test_cc_clear
|
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
cmp.w #0x0080, @neg
|
|
beq .Luwabs16n
|
|
fail
|
|
.Luwabs16n:
|
|
;; Note: leave the value as 0x0080, like it started out.
|
|
|
|
extu_w_abs32_n:
|
|
set_grs_a5a5
|
|
set_ccr_zero
|
|
;; extu.w @aa:32
|
|
extu.w @neg:32
|
|
|
|
;; Test ccr H=0 N=0 Z=0 V=0 C=0
|
|
test_cc_clear
|
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
cmp.w #0x0080, @neg
|
|
beq .Luwabs32n
|
|
fail
|
|
.Luwabs32n:
|
|
;; Note: leave the value as 0x0080, like it started out.
|
|
|
|
.endif
|
|
|
|
pass
|
|
|
|
exit 0
|