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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
308 lines
5.9 KiB
ArmAsm
308 lines
5.9 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp
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// Spec Reference: mmr ppop illegal address
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(gen_int.inc)
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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#ifndef STACKSIZE
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#define STACKSIZE 0x10
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#endif
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#ifndef ITABLE
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#define ITABLE 0xF0000000
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#endif
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GEN_INT_INIT(ITABLE) // set location for interrupt table
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//
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// Reset/Bootstrap Code
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// (Here we set the processor operating modes, initialize registers
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// etc.)
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//
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BOOT:
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INIT_R_REGS(0);
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INIT_P_REGS(0);
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INIT_I_REGS(0); // initialize the dsp address regs
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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//CHECK_INIT(p5, 0xe0000000);
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include(symtable.inc)
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CHECK_INIT_DEF(p5);
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CLI R1; // inhibit events during MMR writes
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LD32_LABEL(sp, USTACK); // setup the user stack pointer
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USP = SP; // and frame pointer
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LD32_LABEL(sp, KSTACK); // setup the stack pointer
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FP = SP; // and frame pointer
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R1 = -1; // Change this to mask interrupts (*)
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CSYNC; // wait for MMR writes to finish
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STI R1; // sync and reenable events (implicit write to IMASK)
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DUMMY:
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R0 = 0 (Z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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SYSCFG = r0;
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RETS = r0; // prevent X's breaking LINK instruction
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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LD32_LABEL(p1, BEGIN);
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LD32(p0, EVT15);
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CLI R1; // inhibit events during write to MMR
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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CSYNC; // wait for it
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STI R1; // reenable events with proper imask
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RAISE 15; // after we RTI, INT 15 should be taken
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LINK 0; // change for how much stack frame space you need.
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[ -- SP ] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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LD32(r0, 0206037020);
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LD32(r1, 0x10070030);
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LD32(r2, 0xe2000043);
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LD32(r3, 0x30305050);
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LD32(r4, 0x0f040860);
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LD32(r5, 0x0a0050d0);
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LD32(r6, 0x00000000);
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LD32(r7, 0x0f060071);
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// LD32(sp, 0xFFE02104);
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// [--sp] = (r7-r6);
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[ -- SP ] = R7;
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[ -- SP ] = R6;
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.dd 0xffff
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R1 += 2;
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CHECKREG(r1, 0x10070034);
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CHECKREG(r2, 0xE2000046);
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CHECKREG(r3, 0x30305054);
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CHECKREG(r4, 0x0f040865);
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CHECKREG(r5, 0x0a0050d6);
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CHECKREG(r6, 0x00000007);
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CHECKREG(r7, 0x0f060079);
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R7 = [ SP ++ ];
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CHECKREG(r7, 0x00000000);
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dbg_pass; // End the test
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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R0 = 2;
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RTN;
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XHANDLE: // Exception Handler 3
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R0 = RETX; // error handler:RETX has the address of the same Illegal instr
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R1 += 2;
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R2 += 3;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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R7 += 8;
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R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr)
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RETX = R0;
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NOP; NOP; NOP; NOP;
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RTX;
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HWHANDLE: // HW Error Handler 5
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R2 = 5;
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RTI;
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THANDLE: // Timer Handler 6
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R3 = 6;
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RTI;
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I7HANDLE: // IVG 7 Handler
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R4 = 7;
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RTI;
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I8HANDLE: // IVG 8 Handler
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R5 = 8;
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RTI;
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I9HANDLE: // IVG 9 Handler
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R6 = 9;
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RTI;
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I10HANDLE: // IVG 10 Handler
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R7 = 10;
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RTI;
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I11HANDLE: // IVG 11 Handler
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R0 = 11;
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RTI;
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I12HANDLE: // IVG 12 Handler
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R1 = 12;
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RTI;
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I13HANDLE: // IVG 13 Handler
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R2 = 13;
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RTI;
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I14HANDLE: // IVG 14 Handler
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R3 = 14;
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RTI;
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I15HANDLE: // IVG 15 Handler
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R4 = 15;
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RTI;
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NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
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//
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// Data Segment
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//
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.section MEM_DATA_ADDR_1,"aw"
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DATA0:
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.dd 0x000a0000
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.dd 0x000b0001
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.dd 0x000c0002
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.dd 0x000d0003
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.dd 0x000e0004
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.dd 0x000f0005
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.dd 0x00100006
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.dd 0x00200007
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.dd 0x00300008
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.dd 0x00400009
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.dd 0x0050000a
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.dd 0x0060000b
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.dd 0x0070000c
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.dd 0x0080000d
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.dd 0x0090000e
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.dd 0x0100000f
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.dd 0x02000010
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.dd 0x03000011
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.dd 0x04000012
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.dd 0x05000013
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.dd 0x06000014
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.dd 0x001a0000
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.dd 0x001b0001
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.dd 0x001c0002
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// Stack Segments (Both Kernel and User)
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.space (STACKSIZE);
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KSTACK:
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.space (STACKSIZE);
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USTACK:
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