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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
166 lines
4.5 KiB
ArmAsm
166 lines
4.5 KiB
ArmAsm
//Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp
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// Spec Reference: Logi2op functions: bittgl
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000000;
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imm32 r1, 0x00000000;
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imm32 r2, 0x00000000;
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imm32 r3, 0x00000000;
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imm32 r4, 0x00000000;
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imm32 r5, 0x00000000;
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imm32 r6, 0x00000000;
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imm32 r7, 0x00000000;
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// bit 0-7
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BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
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BITTGL( R1 , 1 ); /* r1 = 0x00000002 */
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BITTGL( R2 , 2 ); /* r2 = 0x00000004 */
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BITTGL( R3 , 3 ); /* r3 = 0x00000008 */
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BITTGL( R4 , 4 ); /* r4 = 0x00000010 */
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BITTGL( R5 , 5 ); /* r5 = 0x00000020 */
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BITTGL( R6 , 6 ); /* r6 = 0x00000040 */
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BITTGL( R7 , 7 ); /* r7 = 0x00000080 */
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000002;
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CHECKREG r2, 0x00000004;
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CHECKREG r3, 0x00000008;
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CHECKREG r4, 0x00000010;
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CHECKREG r5, 0x00000020;
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CHECKREG r6, 0x00000040;
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CHECKREG r7, 0x00000080;
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// bit 8-15
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BITTGL( R0 , 8 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 9 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 10 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 11 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 12 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 13 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 14 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 15 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x00000101;
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CHECKREG r1, 0x00000202;
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CHECKREG r2, 0x00000404;
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CHECKREG r3, 0x00000808;
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CHECKREG r4, 0x00001010;
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CHECKREG r5, 0x00002020;
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CHECKREG r6, 0x00004040;
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CHECKREG r7, 0x00008080;
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// bit 16-23
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BITTGL( R0 , 16 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 17 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 18 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 19 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 20 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 21 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 22 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 23 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x00010101;
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CHECKREG r1, 0x00020202;
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CHECKREG r2, 0x00040404;
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CHECKREG r3, 0x00080808;
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CHECKREG r4, 0x00101010;
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CHECKREG r5, 0x00202020;
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CHECKREG r6, 0x00404040;
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CHECKREG r7, 0x00808080;
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// bit 24-31
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BITTGL( R0 , 24 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 25 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 26 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 27 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 28 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 29 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 30 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 31 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x01010101;
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CHECKREG r1, 0x02020202;
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CHECKREG r2, 0x04040404;
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CHECKREG r3, 0x08080808;
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CHECKREG r4, 0x10101010;
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CHECKREG r5, 0x20202020;
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CHECKREG r6, 0x40404040;
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CHECKREG r7, 0x80808080;
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// bit 0-7
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BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
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BITTGL( R1 , 1 ); /* r1 = 0x00000002 */
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BITTGL( R2 , 2 ); /* r2 = 0x00000004 */
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BITTGL( R3 , 3 ); /* r3 = 0x00000008 */
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BITTGL( R4 , 4 ); /* r4 = 0x00000010 */
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BITTGL( R5 , 5 ); /* r5 = 0x00000020 */
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BITTGL( R6 , 6 ); /* r6 = 0x00000040 */
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BITTGL( R7 , 7 ); /* r7 = 0x00000080 */
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CHECKREG r0, 0x01010100;
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CHECKREG r1, 0x02020200;
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CHECKREG r2, 0x04040400;
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CHECKREG r3, 0x08080800;
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CHECKREG r4, 0x10101000;
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CHECKREG r5, 0x20202000;
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CHECKREG r6, 0x40404000;
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CHECKREG r7, 0x80808000;
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// bit 8-15
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BITTGL( R0 , 8 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 9 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 10 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 11 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 12 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 13 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 14 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 15 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x01010000;
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CHECKREG r1, 0x02020000;
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CHECKREG r2, 0x04040000;
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CHECKREG r3, 0x08080000;
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CHECKREG r4, 0x10100000;
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CHECKREG r5, 0x20200000;
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CHECKREG r6, 0x40400000;
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CHECKREG r7, 0x80800000;
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// bit 16-23
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BITTGL( R0 , 16 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 17 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 18 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 19 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 20 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 21 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 22 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 23 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x01000000;
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CHECKREG r1, 0x02000000;
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CHECKREG r2, 0x04000000;
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CHECKREG r3, 0x08000000;
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CHECKREG r4, 0x10000000;
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CHECKREG r5, 0x20000000;
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CHECKREG r6, 0x40000000;
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CHECKREG r7, 0x80000000;
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// bit 24-31
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BITTGL( R0 , 24 ); /* r0 = 0x00000100 */
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BITTGL( R1 , 25 ); /* r1 = 0x00000200 */
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BITTGL( R2 , 26 ); /* r2 = 0x00000400 */
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BITTGL( R3 , 27 ); /* r3 = 0x00000800 */
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BITTGL( R4 , 28 ); /* r4 = 0x00001000 */
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BITTGL( R5 , 29 ); /* r5 = 0x00002000 */
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BITTGL( R6 , 30 ); /* r6 = 0x00004000 */
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BITTGL( R7 , 31 ); /* r7 = 0x00008000 */
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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pass
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