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binutils-gdb/gdb/mips-linux-tdep.c
Maciej W. Rozycki 3e29f34a4e MIPS: Keep the ISA bit in compressed code addresses 
1. Background information

The MIPS architecture, as originally designed and implemented in
mid-1980s has a uniform instruction word size that is 4 bytes, naturally
aligned.  As such all MIPS instructions are located at addresses that
have their bits #1 and #0 set to zeroes, and any attempt to execute an
instruction from an address that has any of the two bits set to one
causes an address error exception.  This may for example happen when a
jump-register instruction is executed whose register value used as the
jump target has any of these bits set.

Then in mid 1990s LSI sought a way to improve code density for their
TinyRISC family of MIPS cores and invented an alternatively encoded
instruction set in a joint effort with MIPS Technologies (then a
subsidiary of SGI).  The new instruction set has been named the MIPS16
ASE (Application-Specific Extension) and uses a variable instruction
word size, which is 2 bytes (as the name of the ASE suggests) for most,
but there are a couple of exceptions that take 4 bytes, and then most of
the 2-byte instructions can be treated with a 2-byte extension prefix to
expand the range of the immediate operands used.

As a result instructions are no longer 4-byte aligned, instead they are
aligned to a multiple of 2.  That left the bit #0 still unused for code
references, be it for the standard MIPS (i.e. as originally invented) or
for the MIPS16 instruction set, and based on that observation a clever
trick was invented that on one hand allowed the processor to be
seamlessly switched between the two instruction sets at any time at the
run time while on the other avoided the introduction of any special
control register to do that.

So it is the bit #0 of the instruction address that was chosen as the
selector and named the ISA bit.  Any instruction executed at an even
address is interpreted as a standard MIPS instruction (the address still
has to have its bit #1 clear), any instruction executed at an odd
address is interpreted as a MIPS16 instruction.

To switch between modes ordinary jump instructions are used, such as
used for function calls and returns, specifically the bit #0 of the
source register used in jump-register instructions selects the execution
(ISA) mode for the following piece of code to be interpreted in.
Additionally new jump-immediate instructions were added that flipped the
ISA bit to select the opposite mode upon execution.  They were
considered necessary to avoid the need to make register jumps in all
cases as the original jump-immediate instructions provided no way to
change the bit #0 at all.

This was all important for cases where standard MIPS and MIPS16 code had
to be mixed, either for compatibility with the existing binary code base
or to access resources not reachable from MIPS16 code (the MIPS16
instruction set only provides access to general-purpose registers, and
not for example floating-point unit registers or privileged coprocessor
0 registers) -- pieces of code in the opposite mode can be executed as
ordinary subroutine calls.

A similar approach has been more recently adopted for the MIPS16
replacement instruction set defined as the so called microMIPS ASE.
This is another instruction set encoding introduced to the MIPS
architecture.  Just like the MIPS16 ASE, the microMIPS instruction set
uses a variable-length encoding, where each instruction takes a multiple
of 2 bytes.  The ISA bit has been reused and for microMIPS-capable
processors selects between the standard MIPS and the microMIPS mode
instead.

2. Statement of the problem

To put it shortly, MIPS16 and microMIPS code pointers used by GDB are
different to these observed at the run time.  This results in the same
expressions being evaluated producing different results in GDB and in
the program being debugged.  Obviously it's the results obtained at the
run time that are correct (they define how the program behaves) and
therefore by definition the results obtained in GDB are incorrect.

A bit longer description will record that obviously at the run time the
ISA bit has to be set correctly (refer to background information above
if unsure why so) or the program will not run as expected.  This is
recorded in all the executable file structures used at the run time: the
dynamic symbol table (but not always the static one!), the GOT, and
obviously in all the addresses embedded in code or data of the program
itself, calculated by applying the appropriate relocations at the static
link time.

While a program is being processed by GDB, the ISA bit is stripped off
from any code addresses, presumably to make them the same as the
respective raw memory byte address used by the processor to access the
instruction in the instruction fetch access cycle.  This stripping is
actually performed outside GDB proper, in BFD, specifically
_bfd_mips_elf_symbol_processing (elfxx-mips.c, see the piece of code at
the very bottom of that function, starting with an: "If this is an
odd-valued function symbol, assume it's a MIPS16 or microMIPS one."
comment).

This function is also responsible for symbol table dumps made by
`objdump' too, so you'll never see the ISA bit reported there by that
tool, you need to use `readelf'.

This is however unlike what is ever done at the run time, the ISA bit
once present is never stripped off, for example a cast like this:

(short *) main

will not strip the ISA bit off and if the resulting pointer is intended
to be used to access instructions as data, for example for software
instruction decoding (like for fault recovery or emulation in a signal
handler) or for self-modifying code then the bit still has to be
stripped off by an explicit AND operation.

This is probably best illustrated with a simple real program example.
Let's consider the following simple program:

$ cat foobar.c
int __attribute__ ((mips16)) foo (void)
{
  return 1;
}

int __attribute__ ((mips16)) bar (void)
{
  return 2;
}

int __attribute__ ((nomips16)) foo32 (void)
{
  return 3;
}

int (*foo32p) (void) = foo32;
int (*foop) (void) = foo;
int fooi = (int) foo;

int
main (void)
{
  return foop ();
}
$

This is plain C with no odd tricks, except from the instruction mode
attributes.  They are not necessary to trigger this problem, I just put
them here so that the program can be contained in a single source file
and to make it obvious which function is MIPS16 code and which is not.

Let's try it with Linux, so that everyone can repeat this experiment:

$ mips-linux-gnu-gcc -mips16 -g -O2 -o foobar foobar.c
$

Let's have a look at some interesting symbols:

$ mips-linux-gnu-readelf -s foobar | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 7 entries:
Symbol table '.symtab' contains 95 entries:
    55: 00000000     0 FILE    LOCAL  DEFAULT  ABS foobar.c
    66: 0040068c     4 FUNC    GLOBAL DEFAULT [MIPS16]    12 bar
    68: 00410848     4 OBJECT  GLOBAL DEFAULT   21 foo32p
    70: 00410844     4 OBJECT  GLOBAL DEFAULT   21 foop
    78: 00400684     8 FUNC    GLOBAL DEFAULT   12 foo32
    80: 00400680     4 FUNC    GLOBAL DEFAULT [MIPS16]    12 foo
    88: 00410840     4 OBJECT  GLOBAL DEFAULT   21 fooi
$

Hmm, no sight of the ISA bit, but notice how foo and bar (but not
foo32!) have been marked as MIPS16 functions (ELF symbol structure's
`st_other' field is used for that).

So let's try to run and poke at this program with GDB.  I'll be using a
native system for simplicity (I'll be using ellipses here and there to
remove unrelated clutter):

$ ./foobar
$ echo $?
1
$

So far, so good.

$ gdb ./foobar
[...]
(gdb) break main
Breakpoint 1 at 0x400490: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar

Breakpoint 1, main () at foobar.c:23
23        return foop ();
(gdb)

Yay, it worked!  OK, so let's poke at it:

(gdb) print main
$1 = {int (void)} 0x400490 <main>
(gdb) print foo32
$2 = {int (void)} 0x400684 <foo32>
(gdb) print foo32p
$3 = (int (*)(void)) 0x400684 <foo32>
(gdb) print bar
$4 = {int (void)} 0x40068c <bar>
(gdb) print foo
$5 = {int (void)} 0x400680 <foo>
(gdb) print foop
$6 = (int (*)(void)) 0x400681 <foo>
(gdb)

A-ha!  Here's the difference and finally the ISA bit!

(gdb) print /x fooi
$7 = 0x400681
(gdb) p/x $pc
p/x $pc
$8 = 0x400491
(gdb)

And here as well...

(gdb) advance foo
foo () at foobar.c:4
4       }
(gdb) disassemble
Dump of assembler code for function foo:
   0x00400680 <+0>:     jr      ra
   0x00400682 <+2>:     li      v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0  foo () at foobar.c:4
main () at foobar.c:24
24      }
Value returned is $9 = 1
(gdb) continue
Continuing.
[Inferior 1 (process 14103) exited with code 01]
(gdb)

So let's be a bit inquisitive...

(gdb) run
Starting program: .../foobar

Breakpoint 1, main () at foobar.c:23
23        return foop ();
(gdb)

Actually we do not like to run foo here at all.  Let's run bar instead!

(gdb) set foop = bar
(gdb) print foop
$10 = (int (*)(void)) 0x40068c <bar>
(gdb)

Hmm, no ISA bit.  Is it going to work?

(gdb) advance bar
bar () at foobar.c:9
9       }
(gdb) p/x $pc
$11 = 0x40068c
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068c <+0>:     jr      ra
   0x0040068e <+2>:     li      v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0  bar () at foobar.c:9

Program received signal SIGILL, Illegal instruction.
bar () at foobar.c:9
9       }
(gdb)

Oops!

(gdb) p/x $pc
$12 = 0x40068c
(gdb)

We're still there!

(gdb) continue
Continuing.

Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)

So let's try something else:

(gdb) run
Starting program: .../foobar

Breakpoint 1, main () at foobar.c:23
23        return foop ();
(gdb) set foop = foo
(gdb) advance foo
foo () at foobar.c:4
4       }
(gdb) disassemble
Dump of assembler code for function foo:
=> 0x00400680 <+0>:     jr      ra
   0x00400682 <+2>:     li      v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0  foo () at foobar.c:4

Program received signal SIGILL, Illegal instruction.
foo () at foobar.c:4
4       }
(gdb) continue
Continuing.

Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)

The same problem!

(gdb) run
Starting program:
/net/build2-lucid-cs/scratch/macro/mips-linux-fsf-gcc/isa-bit/foobar

Breakpoint 1, main () at foobar.c:23
23        return foop ();
(gdb) set foop = foo32
(gdb) advance foo32
foo32 () at foobar.c:14
14      }
(gdb) disassemble
Dump of assembler code for function foo32:
=> 0x00400684 <+0>:     jr      ra
   0x00400688 <+4>:     li      v0,3
End of assembler dump.
(gdb) finish
Run till exit from #0  foo32 () at foobar.c:14
main () at foobar.c:24
24      }
Value returned is $14 = 3
(gdb) continue
Continuing.
[Inferior 1 (process 14113) exited with code 03]
(gdb)

That did work though, so it's the ISA bit only!

(gdb) quit

Enough!

That's the tip of the iceberg only though.  So let's rebuild the
executable with some dynamic symbols:

$ mips-linux-gnu-gcc -mips16 -Wl,--export-dynamic -g -O2 -o foobar-dyn foobar.c
$ mips-linux-gnu-readelf -s foobar-dyn | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 32 entries:
     6: 004009cd     4 FUNC    GLOBAL DEFAULT   12 bar
     8: 00410b88     4 OBJECT  GLOBAL DEFAULT   21 foo32p
     9: 00410b84     4 OBJECT  GLOBAL DEFAULT   21 foop
    15: 004009c4     8 FUNC    GLOBAL DEFAULT   12 foo32
    17: 004009c1     4 FUNC    GLOBAL DEFAULT   12 foo
    25: 00410b80     4 OBJECT  GLOBAL DEFAULT   21 fooi
Symbol table '.symtab' contains 95 entries:
    55: 00000000     0 FILE    LOCAL  DEFAULT  ABS foobar.c
    69: 004009cd     4 FUNC    GLOBAL DEFAULT   12 bar
    71: 00410b88     4 OBJECT  GLOBAL DEFAULT   21 foo32p
    72: 00410b84     4 OBJECT  GLOBAL DEFAULT   21 foop
    79: 004009c4     8 FUNC    GLOBAL DEFAULT   12 foo32
    81: 004009c1     4 FUNC    GLOBAL DEFAULT   12 foo
    89: 00410b80     4 OBJECT  GLOBAL DEFAULT   21 fooi
$

OK, now the ISA bit is there for a change, but the MIPS16 `st_other'
attribute gone, hmm...  What does `objdump' do then:

$ mips-linux-gnu-objdump -Tt foobar-dyn | egrep 'SYMBOL|foo|bar'
foobar-dyn:     file format elf32-tradbigmips
SYMBOL TABLE:
00000000 l    df *ABS*  00000000              foobar.c
004009cc g     F .text  00000004              0xf0 bar
00410b88 g     O .data  00000004              foo32p
00410b84 g     O .data  00000004              foop
004009c4 g     F .text  00000008              foo32
004009c0 g     F .text  00000004              0xf0 foo
00410b80 g     O .data  00000004              fooi
DYNAMIC SYMBOL TABLE:
004009cc g    DF .text  00000004  Base        0xf0 bar
00410b88 g    DO .data  00000004  Base        foo32p
00410b84 g    DO .data  00000004  Base        foop
004009c4 g    DF .text  00000008  Base        foo32
004009c0 g    DF .text  00000004  Base        0xf0 foo
00410b80 g    DO .data  00000004  Base        fooi
$

Hmm, the attribute (0xf0, printed raw) is back, and the ISA bit gone
again.

Let's have a look at some DWARF-2 records GDB uses (I'll be stripping
off a lot here for brevity) -- debug info:

$ mips-linux-gnu-readelf -wi foobar
Contents of the .debug_info section:
[...]
  Compilation Unit @ offset 0x88:
   Length:        0xbb (32-bit)
   Version:       4
   Abbrev Offset: 62
   Pointer Size:  4
 <0><93>: Abbrev Number: 1 (DW_TAG_compile_unit)
    <94>   DW_AT_producer    : (indirect string, offset: 0x19e): GNU C 4.8.0 20120513 (experimental) -meb -mips16 -march=mips32r2 -mhard-float -mllsc -mplt -mno-synci -mno-shared -mabi=32 -g -O2
    <98>   DW_AT_language    : 1        (ANSI C)
    <99>   DW_AT_name        : (indirect string, offset: 0x190): foobar.c
    <9d>   DW_AT_comp_dir    : (indirect string, offset: 0x225): [...]
    <a1>   DW_AT_ranges      : 0x0
    <a5>   DW_AT_low_pc      : 0x0
    <a9>   DW_AT_stmt_list   : 0x27
 <1><ad>: Abbrev Number: 2 (DW_TAG_subprogram)
    <ae>   DW_AT_external    : 1
    <ae>   DW_AT_name        : foo
    <b2>   DW_AT_decl_file   : 1
    <b3>   DW_AT_decl_line   : 1
    <b4>   DW_AT_prototyped  : 1
    <b4>   DW_AT_type        : <0xc2>
    <b8>   DW_AT_low_pc      : 0x400680
    <bc>   DW_AT_high_pc     : 0x400684
    <c0>   DW_AT_frame_base  : 1 byte block: 9c         (DW_OP_call_frame_cfa)
    <c2>   DW_AT_GNU_all_call_sites: 1
 <1><c2>: Abbrev Number: 3 (DW_TAG_base_type)
    <c3>   DW_AT_byte_size   : 4
    <c4>   DW_AT_encoding    : 5        (signed)
    <c5>   DW_AT_name        : int
 <1><c9>: Abbrev Number: 4 (DW_TAG_subprogram)
    <ca>   DW_AT_external    : 1
    <ca>   DW_AT_name        : (indirect string, offset: 0x18a): foo32
    <ce>   DW_AT_decl_file   : 1
    <cf>   DW_AT_decl_line   : 11
    <d0>   DW_AT_prototyped  : 1
    <d0>   DW_AT_type        : <0xc2>
    <d4>   DW_AT_low_pc      : 0x400684
    <d8>   DW_AT_high_pc     : 0x40068c
    <dc>   DW_AT_frame_base  : 1 byte block: 9c         (DW_OP_call_frame_cfa)
    <de>   DW_AT_GNU_all_call_sites: 1
 <1><de>: Abbrev Number: 2 (DW_TAG_subprogram)
    <df>   DW_AT_external    : 1
    <df>   DW_AT_name        : bar
    <e3>   DW_AT_decl_file   : 1
    <e4>   DW_AT_decl_line   : 6
    <e5>   DW_AT_prototyped  : 1
    <e5>   DW_AT_type        : <0xc2>
    <e9>   DW_AT_low_pc      : 0x40068c
    <ed>   DW_AT_high_pc     : 0x400690
    <f1>   DW_AT_frame_base  : 1 byte block: 9c         (DW_OP_call_frame_cfa)
    <f3>   DW_AT_GNU_all_call_sites: 1
 <1><f3>: Abbrev Number: 5 (DW_TAG_subprogram)
    <f4>   DW_AT_external    : 1
    <f4>   DW_AT_name        : (indirect string, offset: 0x199): main
    <f8>   DW_AT_decl_file   : 1
    <f9>   DW_AT_decl_line   : 21
    <fa>   DW_AT_prototyped  : 1
    <fa>   DW_AT_type        : <0xc2>
    <fe>   DW_AT_low_pc      : 0x400490
    <102>   DW_AT_high_pc     : 0x4004a4
    <106>   DW_AT_frame_base  : 1 byte block: 9c        (DW_OP_call_frame_cfa)
    <108>   DW_AT_GNU_all_tail_call_sites: 1
[...]
$

-- no sign of the ISA bit anywhere -- frame info:

$ mips-linux-gnu-readelf -wf foobar
[...]
Contents of the .debug_frame section:

00000000 0000000c ffffffff CIE
  Version:               1
  Augmentation:          ""
  Code alignment factor: 1
  Data alignment factor: -4
  Return address column: 31

  DW_CFA_def_cfa_register: r29
  DW_CFA_nop

00000010 0000000c 00000000 FDE cie=00000000 pc=00400680..00400684

00000020 0000000c 00000000 FDE cie=00000000 pc=00400684..0040068c

00000030 0000000c 00000000 FDE cie=00000000 pc=0040068c..00400690

00000040 00000018 00000000 FDE cie=00000000 pc=00400490..004004a4
  DW_CFA_advance_loc: 6 to 00400496
  DW_CFA_def_cfa_offset: 32
  DW_CFA_offset: r31 at cfa-4
  DW_CFA_advance_loc: 6 to 0040049c
  DW_CFA_restore: r31
  DW_CFA_def_cfa_offset: 0
  DW_CFA_nop
  DW_CFA_nop
  DW_CFA_nop
[...]
$

-- no sign of the ISA bit anywhere -- range info (GDB doesn't use arange):

$ mips-linux-gnu-readelf -wR foobar
Contents of the .debug_ranges section:

    Offset   Begin    End
    00000000 00400680 00400690
    00000000 00400490 004004a4
    00000000 <End of list>

$

-- no sign of the ISA bit anywhere -- line info:

$ mips-linux-gnu-readelf -wl foobar
Raw dump of debug contents of section .debug_line:
[...]
  Offset:                      0x27
  Length:                      78
  DWARF Version:               2
  Prologue Length:             31
  Minimum Instruction Length:  1
  Initial value of 'is_stmt':  1
  Line Base:                   -5
  Line Range:                  14
  Opcode Base:                 13

 Opcodes:
  Opcode 1 has 0 args
  Opcode 2 has 1 args
  Opcode 3 has 1 args
  Opcode 4 has 1 args
  Opcode 5 has 1 args
  Opcode 6 has 0 args
  Opcode 7 has 0 args
  Opcode 8 has 0 args
  Opcode 9 has 1 args
  Opcode 10 has 0 args
  Opcode 11 has 0 args
  Opcode 12 has 1 args

 The Directory Table is empty.

 The File Name Table:
  Entry Dir     Time    Size    Name
  1     0       0       0       foobar.c

 Line Number Statements:
  Extended opcode 2: set Address to 0x400681
  Special opcode 6: advance Address by 0 to 0x400681 and Line by 1 to 2
  Special opcode 7: advance Address by 0 to 0x400681 and Line by 2 to 4
  Special opcode 55: advance Address by 3 to 0x400684 and Line by 8 to 12
  Special opcode 7: advance Address by 0 to 0x400684 and Line by 2 to 14
  Advance Line by -7 to 7
  Special opcode 131: advance Address by 9 to 0x40068d and Line by 0 to 7
  Special opcode 7: advance Address by 0 to 0x40068d and Line by 2 to 9
  Advance PC by 3 to 0x400690
  Extended opcode 1: End of Sequence

  Extended opcode 2: set Address to 0x400491
  Advance Line by 21 to 22
  Copy
  Special opcode 6: advance Address by 0 to 0x400491 and Line by 1 to 23
  Special opcode 60: advance Address by 4 to 0x400495 and Line by -1 to 22
  Special opcode 34: advance Address by 2 to 0x400497 and Line by 1 to 23
  Special opcode 62: advance Address by 4 to 0x40049b and Line by 1 to 24
  Special opcode 32: advance Address by 2 to 0x40049d and Line by -1 to 23
  Special opcode 6: advance Address by 0 to 0x40049d and Line by 1 to 24
  Advance PC by 7 to 0x4004a4
  Extended opcode 1: End of Sequence
[...]

-- a-ha, the ISA bit is there!  However it's not always right for some
reason, I don't have a small test case to show it, but here's an excerpt
from MIPS16 libc, a prologue of a function:

00019630 <__libc_init_first>:
   19630:       e8a0            jrc     ra
   19632:       6500            nop

00019634 <_init>:
   19634:       f000 6a11       li      v0,17
   19638:       f7d8 0b08       la      v1,15e00 <_DYNAMIC+0x15c54>
   1963c:       f400 3240       sll     v0,16
   19640:       e269            addu    v0,v1
   19642:       659a            move    gp,v0
   19644:       64f6            save    48,ra,s0-s1
   19646:       671c            move    s0,gp
   19648:       d204            sw      v0,16(sp)
   1964a:       f352 984c       lw      v0,-27828(s0)
   1964e:       6724            move    s1,a0

and the corresponding DWARF-2 line info:

 Line Number Statements:
  Extended opcode 2: set Address to 0x19631
  Advance Line by 44 to 45
  Copy
  Special opcode 8: advance Address by 0 to 0x19631 and Line by 3 to 48
  Special opcode 66: advance Address by 4 to 0x19635 and Line by 5 to 53
  Advance PC by constant 17 to 0x19646
  Special opcode 25: advance Address by 1 to 0x19647 and Line by 6 to 59
  Advance Line by -6 to 53
  Special opcode 33: advance Address by 2 to 0x19649 and Line by 0 to 53
  Special opcode 39: advance Address by 2 to 0x1964b and Line by 6 to 59
  Advance Line by -6 to 53
  Special opcode 61: advance Address by 4 to 0x1964f and Line by 0 to 53

-- see that "Advance PC by constant 17" there?  It clears the ISA bit,
however code at 0x19646 is not standard MIPS code at all.  For some
reason the constant is always 17, I've never seen DW_LNS_const_add_pc
used with any other value -- is that a binutils bug or what?

3. Solution:

I think we should retain the value of the ISA bit in code references,
that is effectively treat them as cookies as they indeed are (although
trivially calculated) rather than raw memory byte addresses.

In a perfect world both the static symbol table and the respective
DWARF-2 records should be fixed to include the ISA bit in all the cases.
I think however that this is infeasible.

All the uses of `_bfd_mips_elf_symbol_processing' can not necessarily be
tracked down.  This function is used by `elf_slurp_symbol_table' that in
turn is used by `bfd_canonicalize_symtab' and
`bfd_canonicalize_dynamic_symtab', which are public interfaces.

Similarly DWARF-2 records are used outside GDB, one notable if a bit
questionable is the exception unwinder (libgcc/unwind-dw2.c) -- I have
identified at least bits in `execute_cfa_program' and
`uw_frame_state_for', both around the calls to `_Unwind_IsSignalFrame',
that would need an update as they effectively flip the ISA bit freely;
see also the comment about MASK_RETURN_ADDR in gcc/config/mips/mips.h.
But there may be more places.  Any change in how DWARF-2 records are
produced would require an update there and would cause compatibility
problems with libgcc.a binaries already distributed; given that this is
a static library a complex change involving function renames would
likely be required.

I propose therefore to accept the existing inconsistencies and deal with
them entirely within GDB.  I have figured out that the ISA bit lost in
various places can still be recovered as long as we have symbol
information -- that'll have the `st_other' attribute correctly set to
one of standard MIPS/MIPS16/microMIPS encoding.

Here's the resulting change.  It adds a couple of new `gdbarch' hooks,
one to update symbol information with the ISA bit lost in
`_bfd_mips_elf_symbol_processing', and two other ones to adjust DWARF-2
records as they're processed.  The ISA bit is set in each address
handled according to information retrieved from the symbol table for the
symbol spanning the address if any; limits are adjusted based on the
address they point to related to the respective base address.
Additionally minimal symbol information has to be adjusted accordingly
in its gdbarch hook.

With these changes in place some complications with ISA bit juggling in
the PC that never fully worked can be removed from the MIPS backend.
Conversely, the generic dynamic linker event special breakpoint symbol
handler has to be updated to call the minimal symbol gdbarch hook to
record that the symbol is a MIPS16 or microMIPS address if applicable or
the breakpoint will be set at the wrong address and either fail to work
or cause SIGTRAPs (this is because the symbol is handled early on and
bypasses regular symbol processing).

4. Results obtained

The change fixes the example above -- to repeat only the crucial steps:

(gdb) break main
Breakpoint 1 at 0x400491: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar

Breakpoint 1, main () at foobar.c:23
23        return foop ();
(gdb) print foo
$1 = {int (void)} 0x400681 <foo>
(gdb) set foop = bar
(gdb) advance bar
bar () at foobar.c:9
9       }
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068d <+0>:     jr      ra
   0x0040068f <+2>:     li      v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0  bar () at foobar.c:9
main () at foobar.c:24
24      }
Value returned is $2 = 2
(gdb) continue
Continuing.
[Inferior 1 (process 14128) exited with code 02]
(gdb)

-- excellent!

The change removes about 90 failures per MIPS16 multilib in mips-sde-elf
testing too, results for MIPS16 are now similar to that for standard
MIPS; microMIPS results are a bit worse because of host-I/O problems in
QEMU used instead of MIPSsim for microMIPS testing only:

                === gdb Summary ===

# of expected passes            14299
# of unexpected failures        187
# of expected failures          56
# of known failures             58
# of unresolved testcases       11
# of untested testcases         52
# of unsupported tests          174

MIPS16:

                === gdb Summary ===

# of expected passes            14298
# of unexpected failures        187
# of unexpected successes       2
# of expected failures          54
# of known failures             58
# of unresolved testcases       12
# of untested testcases         52
# of unsupported tests          174

microMIPS:

                === gdb Summary ===

# of expected passes            14149
# of unexpected failures        201
# of unexpected successes       2
# of expected failures          54
# of known failures             58
# of unresolved testcases       7
# of untested testcases         53
# of unsupported tests          175

2014-12-12  Maciej W. Rozycki  <macro@codesourcery.com>
            Maciej W. Rozycki  <macro@mips.com>
            Pedro Alves  <pedro@codesourcery.com>

	gdb/
	* gdbarch.sh (elf_make_msymbol_special): Change type to `F',
	remove `predefault' and `invalid_p' initializers.
	(make_symbol_special): New architecture method.
	(adjust_dwarf2_addr, adjust_dwarf2_line): Likewise.
	(objfile, symbol): New declarations.
	* arch-utils.h (default_elf_make_msymbol_special): Remove
	prototype.
	(default_make_symbol_special): New prototype.
	(default_adjust_dwarf2_addr): Likewise.
	(default_adjust_dwarf2_line): Likewise.
	* mips-tdep.h (mips_unmake_compact_addr): New prototype.
	* arch-utils.c (default_elf_make_msymbol_special): Remove
	function.
	(default_make_symbol_special): New function.
	(default_adjust_dwarf2_addr): Likewise.
	(default_adjust_dwarf2_line): Likewise.
	* dwarf2-frame.c (decode_frame_entry_1): Call
	`gdbarch_adjust_dwarf2_addr'.
	* dwarf2loc.c (dwarf2_find_location_expression): Likewise.
	* dwarf2read.c (create_addrmap_from_index): Likewise.
	(process_psymtab_comp_unit_reader): Likewise.
	(add_partial_symbol): Likewise.
	(add_partial_subprogram): Likewise.
	(process_full_comp_unit): Likewise.
	(read_file_scope): Likewise.
	(read_func_scope): Likewise.  Call `gdbarch_make_symbol_special'.
	(read_lexical_block_scope): Call `gdbarch_adjust_dwarf2_addr'.
	(read_call_site_scope): Likewise.
	(dwarf2_ranges_read): Likewise.
	(dwarf2_record_block_ranges): Likewise.
	(read_attribute_value): Likewise.
	(dwarf_decode_lines_1): Call `gdbarch_adjust_dwarf2_line'.
	(new_symbol_full): Call `gdbarch_adjust_dwarf2_addr'.
	* elfread.c (elf_symtab_read): Don't call
	`gdbarch_elf_make_msymbol_special' if unset.
	* mips-linux-tdep.c (micromips_linux_sigframe_validate): Strip
	the ISA bit from the PC.
	* mips-tdep.c (mips_unmake_compact_addr): New function.
	(mips_elf_make_msymbol_special): Set the ISA bit in the symbol's
	address appropriately.
	(mips_make_symbol_special): New function.
	(mips_pc_is_mips): Set the ISA bit before symbol lookup.
	(mips_pc_is_mips16): Likewise.
	(mips_pc_is_micromips): Likewise.
	(mips_pc_isa): Likewise.
	(mips_adjust_dwarf2_addr): New function.
	(mips_adjust_dwarf2_line): Likewise.
	(mips_read_pc, mips_unwind_pc): Keep the ISA bit.
	(mips_addr_bits_remove): Likewise.
	(mips_skip_trampoline_code): Likewise.
	(mips_write_pc): Don't set the ISA bit.
	(mips_eabi_push_dummy_call): Likewise.
	(mips_o64_push_dummy_call): Likewise.
	(mips_gdbarch_init): Install `mips_make_symbol_special',
	`mips_adjust_dwarf2_addr' and `mips_adjust_dwarf2_line' gdbarch
	handlers.
	* solib.c (gdb_bfd_lookup_symbol_from_symtab): Get
	target-specific symbol address adjustments.
	* gdbarch.h: Regenerate.
	* gdbarch.c: Regenerate.

2014-12-12  Maciej W. Rozycki  <macro@codesourcery.com>

	gdb/testsuite/
	* gdb.base/func-ptrs.c: New file.
	* gdb.base/func-ptrs.exp: New file.
2014-12-12 13:49:06 +00:00

1773 lines
54 KiB
C
Raw Blame History

/* Target-dependent code for GNU/Linux on MIPS processors.
Copyright (C) 2001-2014 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "gdbcore.h"
#include "target.h"
#include "solib-svr4.h"
#include "osabi.h"
#include "mips-tdep.h"
#include "frame.h"
#include "regcache.h"
#include "trad-frame.h"
#include "tramp-frame.h"
#include "gdbtypes.h"
#include "objfiles.h"
#include "solib.h"
#include "solist.h"
#include "symtab.h"
#include "target-descriptions.h"
#include "regset.h"
#include "mips-linux-tdep.h"
#include "glibc-tdep.h"
#include "linux-tdep.h"
#include "xml-syscall.h"
#include "gdb_signals.h"
static struct target_so_ops mips_svr4_so_ops;
/* This enum represents the signals' numbers on the MIPS
architecture. It just contains the signal definitions which are
different from the generic implementation.
It is derived from the file <arch/mips/include/uapi/asm/signal.h>,
from the Linux kernel tree. */
enum
{
MIPS_LINUX_SIGEMT = 7,
MIPS_LINUX_SIGBUS = 10,
MIPS_LINUX_SIGSYS = 12,
MIPS_LINUX_SIGUSR1 = 16,
MIPS_LINUX_SIGUSR2 = 17,
MIPS_LINUX_SIGCHLD = 18,
MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD,
MIPS_LINUX_SIGPWR = 19,
MIPS_LINUX_SIGWINCH = 20,
MIPS_LINUX_SIGURG = 21,
MIPS_LINUX_SIGIO = 22,
MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO,
MIPS_LINUX_SIGSTOP = 23,
MIPS_LINUX_SIGTSTP = 24,
MIPS_LINUX_SIGCONT = 25,
MIPS_LINUX_SIGTTIN = 26,
MIPS_LINUX_SIGTTOU = 27,
MIPS_LINUX_SIGVTALRM = 28,
MIPS_LINUX_SIGPROF = 29,
MIPS_LINUX_SIGXCPU = 30,
MIPS_LINUX_SIGXFSZ = 31,
MIPS_LINUX_SIGRTMIN = 32,
MIPS_LINUX_SIGRT64 = 64,
MIPS_LINUX_SIGRTMAX = 127,
};
/* Figure out where the longjmp will land.
We expect the first arg to be a pointer to the jmp_buf structure
from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
at. The pc is copied into PC. This routine returns 1 on
success. */
#define MIPS_LINUX_JB_ELEMENT_SIZE 4
#define MIPS_LINUX_JB_PC 0
static int
mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
{
CORE_ADDR jb_addr;
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
if (target_read_memory ((jb_addr
+ MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
return 0;
*pc = extract_unsigned_integer (buf,
gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
byte_order);
return 1;
}
/* Transform the bits comprising a 32-bit register to the right size
for regcache_raw_supply(). This is needed when mips_isa_regsize()
is 8. */
static void
supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[MAX_REGISTER_SIZE];
store_signed_integer (buf, register_size (gdbarch, regnum), byte_order,
extract_signed_integer (addr, 4, byte_order));
regcache_raw_supply (regcache, regnum, buf);
}
/* Unpack an elf_gregset_t into GDB's register cache. */
void
mips_supply_gregset (struct regcache *regcache,
const mips_elf_gregset_t *gregsetp)
{
int regi;
const mips_elf_greg_t *regp = *gregsetp;
char zerobuf[MAX_REGISTER_SIZE];
struct gdbarch *gdbarch = get_regcache_arch (regcache);
memset (zerobuf, 0, MAX_REGISTER_SIZE);
for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
if (mips_linux_restart_reg_p (gdbarch))
supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
regp + EF_CP0_EPC);
supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
regp + EF_CP0_BADVADDR);
supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
regp + EF_CP0_CAUSE);
/* Fill the inaccessible zero register with zero. */
regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
}
static void
mips_supply_gregset_wrapper (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips_elf_gregset_t));
mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
}
/* Pack our registers (or one register) into an elf_gregset_t. */
void
mips_fill_gregset (const struct regcache *regcache,
mips_elf_gregset_t *gregsetp, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int regaddr, regi;
mips_elf_greg_t *regp = *gregsetp;
void *dst;
if (regno == -1)
{
memset (regp, 0, sizeof (mips_elf_gregset_t));
for (regi = 1; regi < 32; regi++)
mips_fill_gregset (regcache, gregsetp, regi);
mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
return;
}
if (regno > 0 && regno < 32)
{
dst = regp + regno + EF_REG0;
regcache_raw_collect (regcache, regno, dst);
return;
}
if (regno == mips_regnum (gdbarch)->lo)
regaddr = EF_LO;
else if (regno == mips_regnum (gdbarch)->hi)
regaddr = EF_HI;
else if (regno == mips_regnum (gdbarch)->pc)
regaddr = EF_CP0_EPC;
else if (regno == mips_regnum (gdbarch)->badvaddr)
regaddr = EF_CP0_BADVADDR;
else if (regno == MIPS_PS_REGNUM)
regaddr = EF_CP0_STATUS;
else if (regno == mips_regnum (gdbarch)->cause)
regaddr = EF_CP0_CAUSE;
else if (mips_linux_restart_reg_p (gdbarch)
&& regno == MIPS_RESTART_REGNUM)
regaddr = EF_REG0;
else
regaddr = -1;
if (regaddr != -1)
{
dst = regp + regaddr;
regcache_raw_collect (regcache, regno, dst);
}
}
static void
mips_fill_gregset_wrapper (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips_elf_gregset_t));
mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
}
/* Likewise, unpack an elf_fpregset_t. */
void
mips_supply_fpregset (struct regcache *regcache,
const mips_elf_fpregset_t *fpregsetp)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int regi;
char zerobuf[MAX_REGISTER_SIZE];
memset (zerobuf, 0, MAX_REGISTER_SIZE);
for (regi = 0; regi < 32; regi++)
regcache_raw_supply (regcache,
gdbarch_fp0_regnum (gdbarch) + regi,
*fpregsetp + regi);
regcache_raw_supply (regcache,
mips_regnum (gdbarch)->fp_control_status,
*fpregsetp + 32);
/* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
regcache_raw_supply (regcache,
mips_regnum (gdbarch)->fp_implementation_revision,
zerobuf);
}
static void
mips_supply_fpregset_wrapper (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips_elf_fpregset_t));
mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
}
/* Likewise, pack one or all floating point registers into an
elf_fpregset_t. */
void
mips_fill_fpregset (const struct regcache *regcache,
mips_elf_fpregset_t *fpregsetp, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
char *to;
if ((regno >= gdbarch_fp0_regnum (gdbarch))
&& (regno < gdbarch_fp0_regnum (gdbarch) + 32))
{
to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
regcache_raw_collect (regcache, regno, to);
}
else if (regno == mips_regnum (gdbarch)->fp_control_status)
{
to = (char *) (*fpregsetp + 32);
regcache_raw_collect (regcache, regno, to);
}
else if (regno == -1)
{
int regi;
for (regi = 0; regi < 32; regi++)
mips_fill_fpregset (regcache, fpregsetp,
gdbarch_fp0_regnum (gdbarch) + regi);
mips_fill_fpregset (regcache, fpregsetp,
mips_regnum (gdbarch)->fp_control_status);
}
}
static void
mips_fill_fpregset_wrapper (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips_elf_fpregset_t));
mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
}
/* Support for 64-bit ABIs. */
/* Figure out where the longjmp will land.
We expect the first arg to be a pointer to the jmp_buf structure
from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
at. The pc is copied into PC. This routine returns 1 on
success. */
/* Details about jmp_buf. */
#define MIPS64_LINUX_JB_PC 0
static int
mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
{
CORE_ADDR jb_addr;
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
buf,
gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
return 0;
*pc = extract_unsigned_integer (buf,
gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
byte_order);
return 1;
}
/* Register set support functions. These operate on standard 64-bit
regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
target will still use the 64-bit format for PTRACE_GETREGS. */
/* Supply a 64-bit register. */
static void
supply_64bit_reg (struct regcache *regcache, int regnum,
const gdb_byte *buf)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& register_size (gdbarch, regnum) == 4)
regcache_raw_supply (regcache, regnum, buf + 4);
else
regcache_raw_supply (regcache, regnum, buf);
}
/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
void
mips64_supply_gregset (struct regcache *regcache,
const mips64_elf_gregset_t *gregsetp)
{
int regi;
const mips64_elf_greg_t *regp = *gregsetp;
gdb_byte zerobuf[MAX_REGISTER_SIZE];
struct gdbarch *gdbarch = get_regcache_arch (regcache);
memset (zerobuf, 0, MAX_REGISTER_SIZE);
for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
(const gdb_byte *) (regp + regi));
if (mips_linux_restart_reg_p (gdbarch))
supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
(const gdb_byte *) (regp + MIPS64_EF_REG0));
supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
(const gdb_byte *) (regp + MIPS64_EF_LO));
supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
(const gdb_byte *) (regp + MIPS64_EF_HI));
supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
(const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
(const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
supply_64bit_reg (regcache, MIPS_PS_REGNUM,
(const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
(const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
/* Fill the inaccessible zero register with zero. */
regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
}
static void
mips64_supply_gregset_wrapper (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips64_elf_gregset_t));
mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
}
/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
void
mips64_fill_gregset (const struct regcache *regcache,
mips64_elf_gregset_t *gregsetp, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int regaddr, regi;
mips64_elf_greg_t *regp = *gregsetp;
void *dst;
if (regno == -1)
{
memset (regp, 0, sizeof (mips64_elf_gregset_t));
for (regi = 1; regi < 32; regi++)
mips64_fill_gregset (regcache, gregsetp, regi);
mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
mips64_fill_gregset (regcache, gregsetp,
mips_regnum (gdbarch)->badvaddr);
mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
return;
}
if (regno > 0 && regno < 32)
regaddr = regno + MIPS64_EF_REG0;
else if (regno == mips_regnum (gdbarch)->lo)
regaddr = MIPS64_EF_LO;
else if (regno == mips_regnum (gdbarch)->hi)
regaddr = MIPS64_EF_HI;
else if (regno == mips_regnum (gdbarch)->pc)
regaddr = MIPS64_EF_CP0_EPC;
else if (regno == mips_regnum (gdbarch)->badvaddr)
regaddr = MIPS64_EF_CP0_BADVADDR;
else if (regno == MIPS_PS_REGNUM)
regaddr = MIPS64_EF_CP0_STATUS;
else if (regno == mips_regnum (gdbarch)->cause)
regaddr = MIPS64_EF_CP0_CAUSE;
else if (mips_linux_restart_reg_p (gdbarch)
&& regno == MIPS_RESTART_REGNUM)
regaddr = MIPS64_EF_REG0;
else
regaddr = -1;
if (regaddr != -1)
{
gdb_byte buf[MAX_REGISTER_SIZE];
LONGEST val;
regcache_raw_collect (regcache, regno, buf);
val = extract_signed_integer (buf, register_size (gdbarch, regno),
byte_order);
dst = regp + regaddr;
store_signed_integer (dst, 8, byte_order, val);
}
}
static void
mips64_fill_gregset_wrapper (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips64_elf_gregset_t));
mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
}
/* Likewise, unpack an elf_fpregset_t. */
void
mips64_supply_fpregset (struct regcache *regcache,
const mips64_elf_fpregset_t *fpregsetp)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int regi;
/* See mips_linux_o32_sigframe_init for a description of the
peculiar FP register layout. */
if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
for (regi = 0; regi < 32; regi++)
{
const gdb_byte *reg_ptr
= (const gdb_byte *) (*fpregsetp + (regi & ~1));
if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
reg_ptr += 4;
regcache_raw_supply (regcache,
gdbarch_fp0_regnum (gdbarch) + regi,
reg_ptr);
}
else
for (regi = 0; regi < 32; regi++)
regcache_raw_supply (regcache,
gdbarch_fp0_regnum (gdbarch) + regi,
(const char *) (*fpregsetp + regi));
supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
(const gdb_byte *) (*fpregsetp + 32));
/* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
include it - but the result of PTRACE_GETFPREGS does. The best we
can do is to assume that its value is present. */
supply_32bit_reg (regcache,
mips_regnum (gdbarch)->fp_implementation_revision,
(const gdb_byte *) (*fpregsetp + 32) + 4);
}
static void
mips64_supply_fpregset_wrapper (const struct regset *regset,
struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips64_elf_fpregset_t));
mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
}
/* Likewise, pack one or all floating point registers into an
elf_fpregset_t. */
void
mips64_fill_fpregset (const struct regcache *regcache,
mips64_elf_fpregset_t *fpregsetp, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte *to;
if ((regno >= gdbarch_fp0_regnum (gdbarch))
&& (regno < gdbarch_fp0_regnum (gdbarch) + 32))
{
/* See mips_linux_o32_sigframe_init for a description of the
peculiar FP register layout. */
if (register_size (gdbarch, regno) == 4)
{
int regi = regno - gdbarch_fp0_regnum (gdbarch);
to = (gdb_byte *) (*fpregsetp + (regi & ~1));
if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
to += 4;
regcache_raw_collect (regcache, regno, to);
}
else
{
to = (gdb_byte *) (*fpregsetp + regno
- gdbarch_fp0_regnum (gdbarch));
regcache_raw_collect (regcache, regno, to);
}
}
else if (regno == mips_regnum (gdbarch)->fp_control_status)
{
gdb_byte buf[MAX_REGISTER_SIZE];
LONGEST val;
regcache_raw_collect (regcache, regno, buf);
val = extract_signed_integer (buf, register_size (gdbarch, regno),
byte_order);
to = (gdb_byte *) (*fpregsetp + 32);
store_signed_integer (to, 4, byte_order, val);
}
else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
{
gdb_byte buf[MAX_REGISTER_SIZE];
LONGEST val;
regcache_raw_collect (regcache, regno, buf);
val = extract_signed_integer (buf, register_size (gdbarch, regno),
byte_order);
to = (gdb_byte *) (*fpregsetp + 32) + 4;
store_signed_integer (to, 4, byte_order, val);
}
else if (regno == -1)
{
int regi;
for (regi = 0; regi < 32; regi++)
mips64_fill_fpregset (regcache, fpregsetp,
gdbarch_fp0_regnum (gdbarch) + regi);
mips64_fill_fpregset (regcache, fpregsetp,
mips_regnum (gdbarch)->fp_control_status);
mips64_fill_fpregset (regcache, fpregsetp,
mips_regnum (gdbarch)->fp_implementation_revision);
}
}
static void
mips64_fill_fpregset_wrapper (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
gdb_assert (len == sizeof (mips64_elf_fpregset_t));
mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
}
static const struct regset mips_linux_gregset =
{
NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper
};
static const struct regset mips64_linux_gregset =
{
NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper
};
static const struct regset mips_linux_fpregset =
{
NULL, mips_supply_fpregset_wrapper, mips_fill_fpregset_wrapper
};
static const struct regset mips64_linux_fpregset =
{
NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper
};
static void
mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
iterate_over_regset_sections_cb *cb,
void *cb_data,
const struct regcache *regcache)
{
if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4)
{
cb (".reg", sizeof (mips_elf_gregset_t), &mips_linux_gregset,
NULL, cb_data);
cb (".reg2", sizeof (mips_elf_fpregset_t), &mips_linux_fpregset,
NULL, cb_data);
}
else
{
cb (".reg", sizeof (mips64_elf_gregset_t), &mips64_linux_gregset,
NULL, cb_data);
cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset,
NULL, cb_data);
}
}
static const struct target_desc *
mips_linux_core_read_description (struct gdbarch *gdbarch,
struct target_ops *target,
bfd *abfd)
{
asection *section = bfd_get_section_by_name (abfd, ".reg");
if (! section)
return NULL;
switch (bfd_section_size (abfd, section))
{
case sizeof (mips_elf_gregset_t):
return mips_tdesc_gp32;
case sizeof (mips64_elf_gregset_t):
return mips_tdesc_gp64;
default:
return NULL;
}
}
/* Check the code at PC for a dynamic linker lazy resolution stub.
GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
section uniformly since version 2.15. If the pc is in that section,
then we are in such a stub. Before that ".stub" was used in 32-bit
ELF binaries, however we do not bother checking for that since we
have never had and that case should be extremely rare these days.
Instead we pattern-match on the code generated by GNU ld. They look
like this:
lw t9,0x8010(gp)
addu t7,ra
jalr t9,ra
addiu t8,zero,INDEX
(with the appropriate doubleword instructions for N64). As any lazy
resolution stubs in microMIPS binaries will always be in a
".MIPS.stubs" section we only ever verify standard MIPS patterns. */
static int
mips_linux_in_dynsym_stub (CORE_ADDR pc)
{
gdb_byte buf[28], *p;
ULONGEST insn, insn1;
int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
if (in_mips_stubs_section (pc))
return 1;
read_memory (pc - 12, buf, 28);
if (n64)
{
/* ld t9,0x8010(gp) */
insn1 = 0xdf998010;
}
else
{
/* lw t9,0x8010(gp) */
insn1 = 0x8f998010;
}
p = buf + 12;
while (p >= buf)
{
insn = extract_unsigned_integer (p, 4, byte_order);
if (insn == insn1)
break;
p -= 4;
}
if (p < buf)
return 0;
insn = extract_unsigned_integer (p + 4, 4, byte_order);
if (n64)
{
/* daddu t7,ra */
if (insn != 0x03e0782d)
return 0;
}
else
{
/* addu t7,ra */
if (insn != 0x03e07821)
return 0;
}
insn = extract_unsigned_integer (p + 8, 4, byte_order);
/* jalr t9,ra */
if (insn != 0x0320f809)
return 0;
insn = extract_unsigned_integer (p + 12, 4, byte_order);
if (n64)
{
/* daddiu t8,zero,0 */
if ((insn & 0xffff0000) != 0x64180000)
return 0;
}
else
{
/* addiu t8,zero,0 */
if ((insn & 0xffff0000) != 0x24180000)
return 0;
}
return 1;
}
/* Return non-zero iff PC belongs to the dynamic linker resolution
code, a PLT entry, or a lazy binding stub. */
static int
mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
{
/* Check whether PC is in the dynamic linker. This also checks
whether it is in the .plt section, used by non-PIC executables. */
if (svr4_in_dynsym_resolve_code (pc))
return 1;
/* Likewise for the stubs. They live in the .MIPS.stubs section these
days, so we check if the PC is within, than fall back to a pattern
match. */
if (mips_linux_in_dynsym_stub (pc))
return 1;
return 0;
}
/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
implementation of this triggers at "fixup" from the same objfile as
"_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
"__dl_runtime_resolve" directly. An unresolved lazy binding
stub will point to _dl_runtime_resolve, which will first call
__dl_runtime_resolve, and then pass control to the resolved
function. */
static CORE_ADDR
mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
{
struct bound_minimal_symbol resolver;
resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc)
return frame_unwind_caller_pc (get_current_frame ());
return glibc_skip_solib_resolver (gdbarch, pc);
}
/* Signal trampoline support. There are four supported layouts for a
signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
n64 rt_sigframe. We handle them all independently; not the most
efficient way, but simplest. First, declare all the unwinders. */
static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func);
static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func);
static int mips_linux_sigframe_validate (const struct tramp_frame *self,
struct frame_info *this_frame,
CORE_ADDR *pc);
static int micromips_linux_sigframe_validate (const struct tramp_frame *self,
struct frame_info *this_frame,
CORE_ADDR *pc);
#define MIPS_NR_LINUX 4000
#define MIPS_NR_N64_LINUX 5000
#define MIPS_NR_N32_LINUX 6000
#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
#define MIPS_INST_SYSCALL 0x0000000c
#define MICROMIPS_INST_LI_V0 0x3040
#define MICROMIPS_INST_POOL32A 0x0000
#define MICROMIPS_INST_SYSCALL 0x8b7c
static const struct tramp_frame mips_linux_o32_sigframe = {
SIGTRAMP_FRAME,
4,
{
{ MIPS_INST_LI_V0_SIGRETURN, -1 },
{ MIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_o32_sigframe_init,
mips_linux_sigframe_validate
};
static const struct tramp_frame mips_linux_o32_rt_sigframe = {
SIGTRAMP_FRAME,
4,
{
{ MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
{ MIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 } },
mips_linux_o32_sigframe_init,
mips_linux_sigframe_validate
};
static const struct tramp_frame mips_linux_n32_rt_sigframe = {
SIGTRAMP_FRAME,
4,
{
{ MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
{ MIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_n32n64_sigframe_init,
mips_linux_sigframe_validate
};
static const struct tramp_frame mips_linux_n64_rt_sigframe = {
SIGTRAMP_FRAME,
4,
{
{ MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
{ MIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_n32n64_sigframe_init,
mips_linux_sigframe_validate
};
static const struct tramp_frame micromips_linux_o32_sigframe = {
SIGTRAMP_FRAME,
2,
{
{ MICROMIPS_INST_LI_V0, -1 },
{ MIPS_NR_sigreturn, -1 },
{ MICROMIPS_INST_POOL32A, -1 },
{ MICROMIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_o32_sigframe_init,
micromips_linux_sigframe_validate
};
static const struct tramp_frame micromips_linux_o32_rt_sigframe = {
SIGTRAMP_FRAME,
2,
{
{ MICROMIPS_INST_LI_V0, -1 },
{ MIPS_NR_rt_sigreturn, -1 },
{ MICROMIPS_INST_POOL32A, -1 },
{ MICROMIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_o32_sigframe_init,
micromips_linux_sigframe_validate
};
static const struct tramp_frame micromips_linux_n32_rt_sigframe = {
SIGTRAMP_FRAME,
2,
{
{ MICROMIPS_INST_LI_V0, -1 },
{ MIPS_NR_N32_rt_sigreturn, -1 },
{ MICROMIPS_INST_POOL32A, -1 },
{ MICROMIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_n32n64_sigframe_init,
micromips_linux_sigframe_validate
};
static const struct tramp_frame micromips_linux_n64_rt_sigframe = {
SIGTRAMP_FRAME,
2,
{
{ MICROMIPS_INST_LI_V0, -1 },
{ MIPS_NR_N64_rt_sigreturn, -1 },
{ MICROMIPS_INST_POOL32A, -1 },
{ MICROMIPS_INST_SYSCALL, -1 },
{ TRAMP_SENTINEL_INSN, -1 }
},
mips_linux_n32n64_sigframe_init,
micromips_linux_sigframe_validate
};
/* *INDENT-OFF* */
/* The unwinder for o32 signal frames. The legacy structures look
like this:
struct sigframe {
u32 sf_ass[4]; [argument save space for o32]
u32 sf_code[2]; [signal trampoline or fill]
struct sigcontext sf_sc;
sigset_t sf_mask;
};
Pre-2.6.12 sigcontext:
struct sigcontext {
unsigned int sc_regmask; [Unused]
unsigned int sc_status;
unsigned long long sc_pc;
unsigned long long sc_regs[32];
unsigned long long sc_fpregs[32];
unsigned int sc_ownedfp;
unsigned int sc_fpc_csr;
unsigned int sc_fpc_eir; [Unused]
unsigned int sc_used_math;
unsigned int sc_ssflags; [Unused]
[Alignment hole of four bytes]
unsigned long long sc_mdhi;
unsigned long long sc_mdlo;
unsigned int sc_cause; [Unused]
unsigned int sc_badvaddr; [Unused]
unsigned long sc_sigset[4]; [kernel's sigset_t]
};
Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
struct sigcontext {
unsigned int sc_regmask; [Unused]
unsigned int sc_status; [Unused]
unsigned long long sc_pc;
unsigned long long sc_regs[32];
unsigned long long sc_fpregs[32];
unsigned int sc_acx;
unsigned int sc_fpc_csr;
unsigned int sc_fpc_eir; [Unused]
unsigned int sc_used_math;
unsigned int sc_dsp;
[Alignment hole of four bytes]
unsigned long long sc_mdhi;
unsigned long long sc_mdlo;
unsigned long sc_hi1;
unsigned long sc_lo1;
unsigned long sc_hi2;
unsigned long sc_lo2;
unsigned long sc_hi3;
unsigned long sc_lo3;
};
The RT signal frames look like this:
struct rt_sigframe {
u32 rs_ass[4]; [argument save space for o32]
u32 rs_code[2] [signal trampoline or fill]
struct siginfo rs_info;
struct ucontext rs_uc;
};
struct ucontext {
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
[Alignment hole of four bytes]
struct sigcontext uc_mcontext;
sigset_t uc_sigmask;
}; */
/* *INDENT-ON* */
#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
#define RTSIGFRAME_SIGINFO_SIZE 128
#define STACK_T_SIZE (3 * 4)
#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ RTSIGFRAME_SIGINFO_SIZE \
+ UCONTEXT_SIGCONTEXT_OFFSET)
#define SIGCONTEXT_PC (1 * 8)
#define SIGCONTEXT_REGS (2 * 8)
#define SIGCONTEXT_FPREGS (34 * 8)
#define SIGCONTEXT_FPCSR (66 * 8 + 4)
#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
#define SIGCONTEXT_HI (69 * 8)
#define SIGCONTEXT_LO (70 * 8)
#define SIGCONTEXT_CAUSE (71 * 8 + 0)
#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
#define SIGCONTEXT_HI1 (71 * 8 + 0)
#define SIGCONTEXT_LO1 (71 * 8 + 4)
#define SIGCONTEXT_HI2 (72 * 8 + 0)
#define SIGCONTEXT_LO2 (72 * 8 + 4)
#define SIGCONTEXT_HI3 (73 * 8 + 0)
#define SIGCONTEXT_LO3 (73 * 8 + 4)
#define SIGCONTEXT_REG_SIZE 8
static void
mips_linux_o32_sigframe_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
int ireg;
CORE_ADDR frame_sp = get_frame_sp (this_frame);
CORE_ADDR sigcontext_base;
const struct mips_regnum *regs = mips_regnum (gdbarch);
CORE_ADDR regs_base;
if (self == &mips_linux_o32_sigframe
|| self == &micromips_linux_o32_sigframe)
sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
else
sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
/* I'm not proud of this hack. Eventually we will have the
infrastructure to indicate the size of saved registers on a
per-frame basis, but right now we don't; the kernel saves eight
bytes but we only want four. Use regs_base to access any
64-bit fields. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
regs_base = sigcontext_base + 4;
else
regs_base = sigcontext_base;
if (mips_linux_restart_reg_p (gdbarch))
trad_frame_set_reg_addr (this_cache,
(MIPS_RESTART_REGNUM
+ gdbarch_num_regs (gdbarch)),
regs_base + SIGCONTEXT_REGS);
for (ireg = 1; ireg < 32; ireg++)
trad_frame_set_reg_addr (this_cache,
(ireg + MIPS_ZERO_REGNUM
+ gdbarch_num_regs (gdbarch)),
(regs_base + SIGCONTEXT_REGS
+ ireg * SIGCONTEXT_REG_SIZE));
/* The way that floating point registers are saved, unfortunately,
depends on the architecture the kernel is built for. For the r3000 and
tx39, four bytes of each register are at the beginning of each of the
32 eight byte slots. For everything else, the registers are saved
using double precision; only the even-numbered slots are initialized,
and the high bits are the odd-numbered register. Assume the latter
layout, since we can't tell, and it's much more common. Which bits are
the "high" bits depends on endianness. */
for (ireg = 0; ireg < 32; ireg++)
if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
trad_frame_set_reg_addr (this_cache,
ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
(sigcontext_base + SIGCONTEXT_FPREGS + 4
+ (ireg & ~1) * SIGCONTEXT_REG_SIZE));
else
trad_frame_set_reg_addr (this_cache,
ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
(sigcontext_base + SIGCONTEXT_FPREGS
+ (ireg & ~1) * SIGCONTEXT_REG_SIZE));
trad_frame_set_reg_addr (this_cache,
regs->pc + gdbarch_num_regs (gdbarch),
regs_base + SIGCONTEXT_PC);
trad_frame_set_reg_addr (this_cache,
(regs->fp_control_status
+ gdbarch_num_regs (gdbarch)),
sigcontext_base + SIGCONTEXT_FPCSR);
if (regs->dspctl != -1)
trad_frame_set_reg_addr (this_cache,
regs->dspctl + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_DSPCTL);
trad_frame_set_reg_addr (this_cache,
regs->hi + gdbarch_num_regs (gdbarch),
regs_base + SIGCONTEXT_HI);
trad_frame_set_reg_addr (this_cache,
regs->lo + gdbarch_num_regs (gdbarch),
regs_base + SIGCONTEXT_LO);
if (regs->dspacc != -1)
{
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_HI1);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_LO1);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_HI2);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_LO2);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_HI3);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_LO3);
}
else
{
trad_frame_set_reg_addr (this_cache,
regs->cause + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_CAUSE);
trad_frame_set_reg_addr (this_cache,
regs->badvaddr + gdbarch_num_regs (gdbarch),
sigcontext_base + SIGCONTEXT_BADVADDR);
}
/* Choice of the bottom of the sigframe is somewhat arbitrary. */
trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
}
/* *INDENT-OFF* */
/* For N32/N64 things look different. There is no non-rt signal frame.
struct rt_sigframe_n32 {
u32 rs_ass[4]; [ argument save space for o32 ]
u32 rs_code[2]; [ signal trampoline or fill ]
struct siginfo rs_info;
struct ucontextn32 rs_uc;
};
struct ucontextn32 {
u32 uc_flags;
s32 uc_link;
stack32_t uc_stack;
struct sigcontext uc_mcontext;
sigset_t uc_sigmask; [ mask last for extensibility ]
};
struct rt_sigframe {
u32 rs_ass[4]; [ argument save space for o32 ]
u32 rs_code[2]; [ signal trampoline ]
struct siginfo rs_info;
struct ucontext rs_uc;
};
struct ucontext {
unsigned long uc_flags;
struct ucontext *uc_link;
stack_t uc_stack;
struct sigcontext uc_mcontext;
sigset_t uc_sigmask; [ mask last for extensibility ]
};
And the sigcontext is different (this is for both n32 and n64):
struct sigcontext {
unsigned long long sc_regs[32];
unsigned long long sc_fpregs[32];
unsigned long long sc_mdhi;
unsigned long long sc_hi1;
unsigned long long sc_hi2;
unsigned long long sc_hi3;
unsigned long long sc_mdlo;
unsigned long long sc_lo1;
unsigned long long sc_lo2;
unsigned long long sc_lo3;
unsigned long long sc_pc;
unsigned int sc_fpc_csr;
unsigned int sc_used_math;
unsigned int sc_dsp;
unsigned int sc_reserved;
};
That is the post-2.6.12 definition of the 64-bit sigcontext; before
then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
included too. */
/* *INDENT-ON* */
#define N32_STACK_T_SIZE STACK_T_SIZE
#define N64_STACK_T_SIZE (2 * 8 + 4)
#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ RTSIGFRAME_SIGINFO_SIZE \
+ N32_UCONTEXT_SIGCONTEXT_OFFSET)
#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ RTSIGFRAME_SIGINFO_SIZE \
+ N64_UCONTEXT_SIGCONTEXT_OFFSET)
#define N64_SIGCONTEXT_REGS (0 * 8)
#define N64_SIGCONTEXT_FPREGS (32 * 8)
#define N64_SIGCONTEXT_HI (64 * 8)
#define N64_SIGCONTEXT_HI1 (65 * 8)
#define N64_SIGCONTEXT_HI2 (66 * 8)
#define N64_SIGCONTEXT_HI3 (67 * 8)
#define N64_SIGCONTEXT_LO (68 * 8)
#define N64_SIGCONTEXT_LO1 (69 * 8)
#define N64_SIGCONTEXT_LO2 (70 * 8)
#define N64_SIGCONTEXT_LO3 (71 * 8)
#define N64_SIGCONTEXT_PC (72 * 8)
#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
#define N64_SIGCONTEXT_REG_SIZE 8
static void
mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
struct frame_info *this_frame,
struct trad_frame_cache *this_cache,
CORE_ADDR func)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
int ireg;
CORE_ADDR frame_sp = get_frame_sp (this_frame);
CORE_ADDR sigcontext_base;
const struct mips_regnum *regs = mips_regnum (gdbarch);
if (self == &mips_linux_n32_rt_sigframe
|| self == &micromips_linux_n32_rt_sigframe)
sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
else
sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
if (mips_linux_restart_reg_p (gdbarch))
trad_frame_set_reg_addr (this_cache,
(MIPS_RESTART_REGNUM
+ gdbarch_num_regs (gdbarch)),
sigcontext_base + N64_SIGCONTEXT_REGS);
for (ireg = 1; ireg < 32; ireg++)
trad_frame_set_reg_addr (this_cache,
(ireg + MIPS_ZERO_REGNUM
+ gdbarch_num_regs (gdbarch)),
(sigcontext_base + N64_SIGCONTEXT_REGS
+ ireg * N64_SIGCONTEXT_REG_SIZE));
for (ireg = 0; ireg < 32; ireg++)
trad_frame_set_reg_addr (this_cache,
ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
(sigcontext_base + N64_SIGCONTEXT_FPREGS
+ ireg * N64_SIGCONTEXT_REG_SIZE));
trad_frame_set_reg_addr (this_cache,
regs->pc + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_PC);
trad_frame_set_reg_addr (this_cache,
(regs->fp_control_status
+ gdbarch_num_regs (gdbarch)),
sigcontext_base + N64_SIGCONTEXT_FPCSR);
trad_frame_set_reg_addr (this_cache,
regs->hi + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_HI);
trad_frame_set_reg_addr (this_cache,
regs->lo + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_LO);
if (regs->dspacc != -1)
{
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_HI1);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_LO1);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_HI2);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_LO2);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_HI3);
trad_frame_set_reg_addr (this_cache,
regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_LO3);
}
if (regs->dspctl != -1)
trad_frame_set_reg_addr (this_cache,
regs->dspctl + gdbarch_num_regs (gdbarch),
sigcontext_base + N64_SIGCONTEXT_DSPCTL);
/* Choice of the bottom of the sigframe is somewhat arbitrary. */
trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
}
/* Implement struct tramp_frame's "validate" method for standard MIPS code. */
static int
mips_linux_sigframe_validate (const struct tramp_frame *self,
struct frame_info *this_frame,
CORE_ADDR *pc)
{
return mips_pc_is_mips (*pc);
}
/* Implement struct tramp_frame's "validate" method for microMIPS code. */
static int
micromips_linux_sigframe_validate (const struct tramp_frame *self,
struct frame_info *this_frame,
CORE_ADDR *pc)
{
if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc))
{
*pc = mips_unmake_compact_addr (*pc);
return 1;
}
else
return 0;
}
/* Implement the "write_pc" gdbarch method. */
static void
mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
mips_write_pc (regcache, pc);
/* Clear the syscall restart flag. */
if (mips_linux_restart_reg_p (gdbarch))
regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
}
/* Return 1 if MIPS_RESTART_REGNUM is usable. */
int
mips_linux_restart_reg_p (struct gdbarch *gdbarch)
{
/* If we do not have a target description with registers, then
MIPS_RESTART_REGNUM will not be included in the register set. */
if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
return 0;
/* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
either be GPR-sized or missing. */
return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
}
/* When FRAME is at a syscall instruction, return the PC of the next
instruction to be executed. */
static CORE_ADDR
mips_linux_syscall_next_pc (struct frame_info *frame)
{
CORE_ADDR pc = get_frame_pc (frame);
ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
/* If we are about to make a sigreturn syscall, use the unwinder to
decode the signal frame. */
if (v0 == MIPS_NR_sigreturn
|| v0 == MIPS_NR_rt_sigreturn
|| v0 == MIPS_NR_N64_rt_sigreturn
|| v0 == MIPS_NR_N32_rt_sigreturn)
return frame_unwind_caller_pc (get_current_frame ());
return pc + 4;
}
/* Return the current system call's number present in the
v0 register. When the function fails, it returns -1. */
static LONGEST
mips_linux_get_syscall_number (struct gdbarch *gdbarch,
ptid_t ptid)
{
struct regcache *regcache = get_thread_regcache (ptid);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
/* The content of a register */
gdb_byte buf[8];
/* The result */
LONGEST ret;
/* Make sure we're in a known ABI */
gdb_assert (tdep->mips_abi == MIPS_ABI_O32
|| tdep->mips_abi == MIPS_ABI_N32
|| tdep->mips_abi == MIPS_ABI_N64);
gdb_assert (regsize <= sizeof (buf));
/* Getting the system call number from the register.
syscall number is in v0 or $2. */
regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
ret = extract_signed_integer (buf, regsize, byte_order);
return ret;
}
/* Implementation of `gdbarch_gdb_signal_to_target', as defined in
gdbarch.h. */
static int
mips_gdb_signal_to_target (struct gdbarch *gdbarch,
enum gdb_signal signal)
{
switch (signal)
{
case GDB_SIGNAL_EMT:
return MIPS_LINUX_SIGEMT;
case GDB_SIGNAL_BUS:
return MIPS_LINUX_SIGBUS;
case GDB_SIGNAL_SYS:
return MIPS_LINUX_SIGSYS;
case GDB_SIGNAL_USR1:
return MIPS_LINUX_SIGUSR1;
case GDB_SIGNAL_USR2:
return MIPS_LINUX_SIGUSR2;
case GDB_SIGNAL_CHLD:
return MIPS_LINUX_SIGCHLD;
case GDB_SIGNAL_PWR:
return MIPS_LINUX_SIGPWR;
case GDB_SIGNAL_WINCH:
return MIPS_LINUX_SIGWINCH;
case GDB_SIGNAL_URG:
return MIPS_LINUX_SIGURG;
case GDB_SIGNAL_IO:
return MIPS_LINUX_SIGIO;
case GDB_SIGNAL_POLL:
return MIPS_LINUX_SIGPOLL;
case GDB_SIGNAL_STOP:
return MIPS_LINUX_SIGSTOP;
case GDB_SIGNAL_TSTP:
return MIPS_LINUX_SIGTSTP;
case GDB_SIGNAL_CONT:
return MIPS_LINUX_SIGCONT;
case GDB_SIGNAL_TTIN:
return MIPS_LINUX_SIGTTIN;
case GDB_SIGNAL_TTOU:
return MIPS_LINUX_SIGTTOU;
case GDB_SIGNAL_VTALRM:
return MIPS_LINUX_SIGVTALRM;
case GDB_SIGNAL_PROF:
return MIPS_LINUX_SIGPROF;
case GDB_SIGNAL_XCPU:
return MIPS_LINUX_SIGXCPU;
case GDB_SIGNAL_XFSZ:
return MIPS_LINUX_SIGXFSZ;
/* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>,
therefore we have to handle it here. */
case GDB_SIGNAL_REALTIME_32:
return MIPS_LINUX_SIGRTMIN;
}
if (signal >= GDB_SIGNAL_REALTIME_33
&& signal <= GDB_SIGNAL_REALTIME_63)
{
int offset = signal - GDB_SIGNAL_REALTIME_33;
return MIPS_LINUX_SIGRTMIN + 1 + offset;
}
else if (signal >= GDB_SIGNAL_REALTIME_64
&& signal <= GDB_SIGNAL_REALTIME_127)
{
int offset = signal - GDB_SIGNAL_REALTIME_64;
return MIPS_LINUX_SIGRT64 + offset;
}
return linux_gdb_signal_to_target (gdbarch, signal);
}
/* Translate signals based on MIPS signal values.
Adapted from gdb/common/signals.c. */
static enum gdb_signal
mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal)
{
switch (signal)
{
case MIPS_LINUX_SIGEMT:
return GDB_SIGNAL_EMT;
case MIPS_LINUX_SIGBUS:
return GDB_SIGNAL_BUS;
case MIPS_LINUX_SIGSYS:
return GDB_SIGNAL_SYS;
case MIPS_LINUX_SIGUSR1:
return GDB_SIGNAL_USR1;
case MIPS_LINUX_SIGUSR2:
return GDB_SIGNAL_USR2;
case MIPS_LINUX_SIGCHLD:
return GDB_SIGNAL_CHLD;
case MIPS_LINUX_SIGPWR:
return GDB_SIGNAL_PWR;
case MIPS_LINUX_SIGWINCH:
return GDB_SIGNAL_WINCH;
case MIPS_LINUX_SIGURG:
return GDB_SIGNAL_URG;
/* No way to differentiate between SIGIO and SIGPOLL.
Therefore, we just handle the first one. */
case MIPS_LINUX_SIGIO:
return GDB_SIGNAL_IO;
case MIPS_LINUX_SIGSTOP:
return GDB_SIGNAL_STOP;
case MIPS_LINUX_SIGTSTP:
return GDB_SIGNAL_TSTP;
case MIPS_LINUX_SIGCONT:
return GDB_SIGNAL_CONT;
case MIPS_LINUX_SIGTTIN:
return GDB_SIGNAL_TTIN;
case MIPS_LINUX_SIGTTOU:
return GDB_SIGNAL_TTOU;
case MIPS_LINUX_SIGVTALRM:
return GDB_SIGNAL_VTALRM;
case MIPS_LINUX_SIGPROF:
return GDB_SIGNAL_PROF;
case MIPS_LINUX_SIGXCPU:
return GDB_SIGNAL_XCPU;
case MIPS_LINUX_SIGXFSZ:
return GDB_SIGNAL_XFSZ;
}
if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX)
{
/* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
int offset = signal - MIPS_LINUX_SIGRTMIN;
if (offset == 0)
return GDB_SIGNAL_REALTIME_32;
else if (offset < 32)
return (enum gdb_signal) (offset - 1
+ (int) GDB_SIGNAL_REALTIME_33);
else
return (enum gdb_signal) (offset - 32
+ (int) GDB_SIGNAL_REALTIME_64);
}
return linux_gdb_signal_from_target (gdbarch, signal);
}
/* Initialize one of the GNU/Linux OS ABIs. */
static void
mips_linux_init_abi (struct gdbarch_info info,
struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum mips_abi abi = mips_abi (gdbarch);
struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
linux_init_abi (info, gdbarch);
/* Get the syscall number from the arch's register. */
set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
switch (abi)
{
case MIPS_ABI_O32:
set_gdbarch_get_longjmp_target (gdbarch,
mips_linux_get_longjmp_target);
set_solib_svr4_fetch_link_map_offsets
(gdbarch, svr4_ilp32_fetch_link_map_offsets);
tramp_frame_prepend_unwinder (gdbarch, &micromips_linux_o32_sigframe);
tramp_frame_prepend_unwinder (gdbarch,
&micromips_linux_o32_rt_sigframe);
tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml");
break;
case MIPS_ABI_N32:
set_gdbarch_get_longjmp_target (gdbarch,
mips_linux_get_longjmp_target);
set_solib_svr4_fetch_link_map_offsets
(gdbarch, svr4_ilp32_fetch_link_map_offsets);
set_gdbarch_long_double_bit (gdbarch, 128);
/* These floatformats should probably be renamed. MIPS uses
the same 128-bit IEEE floating point format that IA-64 uses,
except that the quiet/signalling NaN bit is reversed (GDB
does not distinguish between quiet and signalling NaNs). */
set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
tramp_frame_prepend_unwinder (gdbarch,
&micromips_linux_n32_rt_sigframe);
tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml");
break;
case MIPS_ABI_N64:
set_gdbarch_get_longjmp_target (gdbarch,
mips64_linux_get_longjmp_target);
set_solib_svr4_fetch_link_map_offsets
(gdbarch, svr4_lp64_fetch_link_map_offsets);
set_gdbarch_long_double_bit (gdbarch, 128);
/* These floatformats should probably be renamed. MIPS uses
the same 128-bit IEEE floating point format that IA-64 uses,
except that the quiet/signalling NaN bit is reversed (GDB
does not distinguish between quiet and signalling NaNs). */
set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
tramp_frame_prepend_unwinder (gdbarch,
&micromips_linux_n64_rt_sigframe);
tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml");
break;
default:
break;
}
set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
/* Enable TLS support. */
set_gdbarch_fetch_tls_load_module_address (gdbarch,
svr4_fetch_objfile_link_map);
/* Initialize this lazily, to avoid an initialization order
dependency on solib-svr4.c's _initialize routine. */
if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
{
mips_svr4_so_ops = svr4_so_ops;
mips_svr4_so_ops.in_dynsym_resolve_code
= mips_linux_in_dynsym_resolve_code;
}
set_solib_ops (gdbarch, &mips_svr4_so_ops);
set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
set_gdbarch_core_read_description (gdbarch,
mips_linux_core_read_description);
set_gdbarch_iterate_over_regset_sections
(gdbarch, mips_linux_iterate_over_regset_sections);
set_gdbarch_gdb_signal_from_target (gdbarch,
mips_gdb_signal_from_target);
set_gdbarch_gdb_signal_to_target (gdbarch,
mips_gdb_signal_to_target);
tdep->syscall_next_pc = mips_linux_syscall_next_pc;
if (tdesc_data)
{
const struct tdesc_feature *feature;
/* If we have target-described registers, then we can safely
reserve a number for MIPS_RESTART_REGNUM (whether it is
described or not). */
gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
/* If it's present, then assign it to the reserved number. */
feature = tdesc_find_feature (info.target_desc,
"org.gnu.gdb.mips.linux");
if (feature != NULL)
tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
"restart");
}
}
/* Provide a prototype to silence -Wmissing-prototypes. */
extern initialize_file_ftype _initialize_mips_linux_tdep;
void
_initialize_mips_linux_tdep (void)
{
const struct bfd_arch_info *arch_info;
for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
arch_info != NULL;
arch_info = arch_info->next)
{
gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
GDB_OSABI_LINUX,
mips_linux_init_abi);
}
}
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