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2_10-branch'. Sprout from cygnus 2000-02-22 16:18:13 UTC Ian Lance Taylor <ian@airs.com> 'import libiberty from egcs' Cherrypick from master 2000-04-02 08:24:54 UTC Richard Henderson <rth@redhat.com> ' * config/tc-d30v.c (check_range): Allow signed or unsigned 32-bit': ChangeLog Makefile.in bfd/ChangeLog bfd/Makefile.am bfd/Makefile.in bfd/acinclude.m4 bfd/aclocal.m4 bfd/aix386-core.c bfd/aout-adobe.c bfd/aout-arm.c bfd/aout-ns32k.c bfd/aout-target.h bfd/aout-tic30.c bfd/aoutx.h bfd/archive.c bfd/archures.c bfd/armnetbsd.c bfd/bfd-in.h bfd/bfd-in2.h bfd/bfd.c bfd/binary.c bfd/bout.c bfd/cisco-core.c bfd/coff-a29k.c bfd/coff-alpha.c bfd/coff-apollo.c bfd/coff-arm.c bfd/coff-go32.c bfd/coff-h8300.c bfd/coff-h8500.c bfd/coff-i386.c bfd/coff-i860.c bfd/coff-i960.c bfd/coff-m68k.c bfd/coff-m88k.c bfd/coff-mcore.c bfd/coff-mips.c bfd/coff-ppc.c bfd/coff-rs6000.c bfd/coff-sh.c bfd/coff-sparc.c bfd/coff-stgo32.c bfd/coff-tic30.c bfd/coff-tic80.c bfd/coff-w65.c bfd/coff-we32k.c bfd/coff-z8k.c bfd/coffcode.h bfd/coffgen.c bfd/cofflink.c bfd/coffswap.h bfd/config.bfd bfd/config.in bfd/configure bfd/configure.host bfd/configure.in bfd/cpu-arm.c bfd/cpu-avr.c bfd/cpu-d10v.c bfd/cpu-h8500.c bfd/cpu-hppa.c bfd/cpu-i370.c bfd/cpu-m10300.c bfd/cpu-m32r.c bfd/cpu-mcore.c bfd/cpu-ns32k.c bfd/cpu-pj.c bfd/cpu-sh.c bfd/cpu-w65.c bfd/doc/Makefile.in bfd/dwarf1.c bfd/dwarf2.c bfd/ecoff.c bfd/ecofflink.c bfd/elf-bfd.h bfd/elf-hppa.h bfd/elf-m10200.c bfd/elf-m10300.c bfd/elf.c bfd/elf32-arc.c bfd/elf32-arm.h bfd/elf32-avr.c bfd/elf32-d10v.c bfd/elf32-d30v.c bfd/elf32-fr30.c bfd/elf32-gen.c bfd/elf32-hppa.c bfd/elf32-hppa.h bfd/elf32-i370.c bfd/elf32-i386.c bfd/elf32-i860.c bfd/elf32-i960.c bfd/elf32-m32r.c bfd/elf32-m68k.c bfd/elf32-m88k.c bfd/elf32-mcore.c bfd/elf32-mips.c bfd/elf32-pj.c bfd/elf32-ppc.c bfd/elf32-sh.c bfd/elf32-sparc.c bfd/elf32-v850.c bfd/elf64-alpha.c bfd/elf64-gen.c bfd/elf64-mips.c bfd/elf64-sparc.c bfd/elfarm-nabi.c bfd/elfarm-oabi.c bfd/elfcode.h bfd/elflink.c bfd/elflink.h bfd/elfxx-target.h bfd/epoc-pe-arm.c bfd/epoc-pei-arm.c bfd/freebsd.h bfd/hash.c bfd/hosts/alphalinux.h bfd/hp300hpux.c bfd/hppabsd-core.c bfd/hpux-core.c bfd/i386linux.c bfd/i386lynx.c bfd/i386msdos.c bfd/i386os9k.c bfd/ieee.c bfd/ihex.c bfd/irix-core.c bfd/libbfd-in.h bfd/libbfd.c bfd/libbfd.h bfd/libcoff-in.h bfd/libcoff.h bfd/libecoff.h bfd/libhppa.h bfd/libpei.h bfd/linker.c bfd/m68klinux.c bfd/mipsbsd.c bfd/netbsd-core.c bfd/netbsd.h bfd/nlm-target.h bfd/nlm32-ppc.c bfd/nlm32-sparc.c bfd/nlmcode.h bfd/oasys.c bfd/osf-core.c bfd/pc532-mach.c bfd/pe-arm.c bfd/pe-i386.c bfd/pe-mips.c bfd/pe-ppc.c bfd/pe-sh.c bfd/pei-arm.c bfd/pei-i386.c bfd/pei-mcore.c bfd/pei-mips.c bfd/pei-ppc.c bfd/pei-sh.c bfd/peicode.h bfd/peigen.c bfd/po/POTFILES.in bfd/po/bfd.pot bfd/ppcboot.c bfd/ptrace-core.c bfd/reloc.c bfd/reloc16.c bfd/riscix.c bfd/rs6000-core.c bfd/sco5-core.c bfd/section.c bfd/som.c bfd/sparclinux.c bfd/srec.c bfd/stabs.c bfd/sunos.c bfd/syms.c bfd/targets.c bfd/tekhex.c bfd/trad-core.c bfd/versados.c bfd/vms-gsd.c bfd/vms-hdr.c bfd/vms-misc.c bfd/vms-tir.c bfd/vms.c bfd/vms.h bfd/xcofflink.c binutils/ChangeLog binutils/Makefile.am binutils/Makefile.in binutils/NEWS binutils/aclocal.m4 binutils/addr2line.c binutils/ar.1 binutils/ar.c binutils/arparse.y binutils/arsup.c binutils/binutils.texi binutils/config.in binutils/configure binutils/configure.in binutils/debug.c binutils/deflex.l binutils/defparse.y binutils/dlltool.c binutils/dllwrap.c binutils/dyn-string.c binutils/dyn-string.h binutils/filemode.c binutils/ieee.c binutils/nm.c binutils/objcopy.1 binutils/objcopy.c binutils/objdump.c binutils/po/POTFILES.in binutils/po/binutils.pot binutils/prdbg.c binutils/rclex.l binutils/rcparse.y binutils/rdcoff.c binutils/rddbg.c binutils/readelf.c binutils/rename.c binutils/rescoff.c binutils/resrc.c binutils/resres.c binutils/size.c binutils/stabs.c binutils/strings.1 binutils/strings.c binutils/testsuite/ChangeLog binutils/testsuite/binutils-all/hppa/freg.s binutils/testsuite/binutils-all/hppa/objdump.exp binutils/testsuite/binutils-all/objcopy.exp binutils/testsuite/binutils-all/objdump.exp binutils/testsuite/binutils-all/readelf.h binutils/testsuite/binutils-all/readelf.r binutils/testsuite/binutils-all/readelf.s binutils/testsuite/binutils-all/readelf.ss binutils/testsuite/binutils-all/readelf.wi binutils/testsuite/binutils-all/testprog.c binutils/windres.c binutils/windres.h binutils/wrstabs.c config.guess config.sub config/ChangeLog config/mh-i370pic config/mt-aix43 config/mt-i370pic config/mt-wince configure configure.in gas/ChangeLog gas/Makefile.am gas/Makefile.in gas/NEWS gas/aclocal.m4 gas/app.c gas/as.c gas/as.h gas/atof-generic.c gas/cgen.c gas/cond.c gas/config/atof-ieee.c gas/config/atof-vax.c gas/config/e-i386aout.c gas/config/m68k-parse.h gas/config/obj-aout.c gas/config/obj-aout.h gas/config/obj-bout.c gas/config/obj-coff.c gas/config/obj-coff.h gas/config/obj-ecoff.c gas/config/obj-ecoff.h gas/config/obj-elf.c gas/config/obj-elf.h gas/config/obj-evax.h gas/config/obj-multi.h gas/config/obj-som.c gas/config/obj-vms.h gas/config/tc-alpha.c gas/config/tc-alpha.h gas/config/tc-arc.c gas/config/tc-arc.h gas/config/tc-arm.c gas/config/tc-arm.h gas/config/tc-avr.c gas/config/tc-avr.h gas/config/tc-d10v.c gas/config/tc-d10v.h gas/config/tc-d30v.c gas/config/tc-d30v.h gas/config/tc-fr30.c gas/config/tc-h8300.c gas/config/tc-hppa.c gas/config/tc-hppa.h gas/config/tc-i370.c gas/config/tc-i370.h gas/config/tc-i386.c gas/config/tc-i386.h gas/config/tc-i860.c gas/config/tc-i960.c gas/config/tc-i960.h gas/config/tc-m32r.c gas/config/tc-m68k.c gas/config/tc-m68k.h gas/config/tc-m88k.c gas/config/tc-m88k.h gas/config/tc-mcore.c gas/config/tc-mcore.h gas/config/tc-mips.c gas/config/tc-mips.h gas/config/tc-mn10200.c gas/config/tc-mn10300.c gas/config/tc-ns32k.c gas/config/tc-ns32k.h gas/config/tc-pj.c gas/config/tc-pj.h gas/config/tc-ppc.c gas/config/tc-ppc.h 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include/coff/pe.h include/coff/sh.h include/dis-asm.h include/elf/ChangeLog include/elf/arm-oabi.h include/elf/arm.h include/elf/avr.h include/elf/common.h include/elf/dwarf.h include/elf/dwarf2.h include/elf/hppa.h include/elf/i370.h include/elf/i386.h include/elf/i960.h include/elf/m32r.h include/elf/m68k.h include/elf/mcore.h include/elf/mips.h include/elf/mn10300.h include/elf/pj.h include/elf/reloc-macros.h include/elf/sh.h include/elf/sparc.h include/hashtab.h include/hp-symtab.h include/opcode/ChangeLog include/opcode/alpha.h include/opcode/cgen.h include/opcode/d10v.h include/opcode/d30v.h include/opcode/hppa.h include/opcode/i370.h include/opcode/i386.h include/opcode/m68k.h include/opcode/mips.h include/opcode/mn10300.h include/opcode/pj.h include/opcode/ppc.h include/partition.h include/remote-sim.h include/sim-d10v.h ld/ChangeLog ld/Makefile.am ld/Makefile.in ld/NEWS ld/aclocal.m4 ld/config.in ld/configure ld/configure.host ld/configure.in ld/configure.tgt ld/deffile.h ld/deffilep.y ld/emulparams/arm_epoc_pe.sh ld/emulparams/armelf.sh ld/emulparams/armelf_linux.sh ld/emulparams/armelf_linux26.sh ld/emulparams/armelf_oabi.sh ld/emulparams/armnbsd.sh ld/emulparams/armpe.sh ld/emulparams/avr1200.sh ld/emulparams/avr23xx.sh ld/emulparams/avr4433.sh ld/emulparams/avr44x4.sh ld/emulparams/avr85xx.sh ld/emulparams/avrmega103.sh ld/emulparams/avrmega161.sh ld/emulparams/avrmega603.sh ld/emulparams/d10velf.sh ld/emulparams/elf32_i960.sh ld/emulparams/elf32bmipn32.sh ld/emulparams/elf32i370.sh ld/emulparams/elf32mcore.sh ld/emulparams/elf32ppc.sh ld/emulparams/elf32ppclinux.sh ld/emulparams/elf64_sparc.sh ld/emulparams/elf64bmip.sh ld/emulparams/elf64hppa.sh ld/emulparams/i386pe.sh ld/emulparams/i386pe_posix.sh ld/emulparams/mcorepe.sh ld/emulparams/mipspe.sh ld/emulparams/pjelf.sh ld/emulparams/pjlelf.sh ld/emulparams/ppcpe.sh ld/emulparams/shpe.sh ld/emultempl/aix.em ld/emultempl/armcoff.em ld/emultempl/armelf.em ld/emultempl/armelf_oabi.em ld/emultempl/astring.sed ld/emultempl/beos.em ld/emultempl/elf32.em ld/emultempl/generic.em ld/emultempl/gld960.em ld/emultempl/gld960c.em ld/emultempl/hppaelf.em ld/emultempl/linux.em ld/emultempl/lnk960.em ld/emultempl/mipsecoff.em ld/emultempl/ostring.sed ld/emultempl/pe.em ld/emultempl/sunos.em ld/emultempl/vanilla.em ld/genscripts.sh ld/ld.h ld/ld.texinfo ld/ldcref.c ld/ldemul.c ld/ldemul.h ld/ldexp.c ld/ldfile.c ld/ldfile.h ld/ldgram.y ld/ldlang.c ld/ldlang.h ld/ldmain.c ld/ldmisc.c ld/lexsup.c ld/mri.c ld/pe-dll.c ld/pe-dll.h ld/po/POTFILES.in ld/po/ld.pot ld/scripttempl/armcoff.sc ld/scripttempl/elf.sc ld/scripttempl/elf32avr.sc ld/scripttempl/elfd10v.sc ld/scripttempl/elfi370.sc ld/scripttempl/epocpe.sc ld/scripttempl/i386go32.sc ld/scripttempl/mcorepe.sc ld/scripttempl/pe.sc ld/scripttempl/pj.sc ld/scripttempl/v850.sc ld/testsuite/ChangeLog ld/testsuite/ld-cdtest/cdtest-foo.cc ld/testsuite/ld-cdtest/cdtest-main.cc ld/testsuite/ld-checks/asm.s ld/testsuite/ld-checks/checks.exp ld/testsuite/ld-elfvers/vers.exp ld/testsuite/ld-elfvers/vers1.c ld/testsuite/ld-elfvers/vers15.c ld/testsuite/ld-elfvers/vers17.c ld/testsuite/ld-elfvers/vers17.dsym ld/testsuite/ld-elfvers/vers17.map ld/testsuite/ld-elfvers/vers17.ver ld/testsuite/ld-elfvers/vers18.c ld/testsuite/ld-elfvers/vers18.dsym ld/testsuite/ld-elfvers/vers18.map ld/testsuite/ld-elfvers/vers18.sym ld/testsuite/ld-elfvers/vers18.ver ld/testsuite/ld-elfvers/vers19.c ld/testsuite/ld-elfvers/vers19.dsym ld/testsuite/ld-elfvers/vers19.ver ld/testsuite/ld-elfvers/vers2.c ld/testsuite/ld-elfvers/vers3.c ld/testsuite/ld-elfvers/vers4.c ld/testsuite/ld-elfvers/vers6.c ld/testsuite/ld-elfvers/vers7.c ld/testsuite/ld-elfvers/vers9.c ld/testsuite/ld-scripts/phdrs.exp ld/testsuite/ld-scripts/phdrs.t ld/testsuite/ld-scripts/script.exp ld/testsuite/ld-scripts/weak.exp ld/testsuite/ld-selective/selective.exp ld/testsuite/ld-shared/main.c ld/testsuite/ld-shared/sh1.c ld/testsuite/ld-shared/shared.exp ld/testsuite/ld-srec/sr3.cc ld/testsuite/ld-srec/srec.exp ld/testsuite/ld-undefined/undefined.exp ld/testsuite/lib/ld-lib.exp libiberty/ChangeLog libiberty/Makefile.in libiberty/argv.c libiberty/choose-temp.c libiberty/config.in libiberty/configure libiberty/configure.in libiberty/cplus-dem.c libiberty/floatformat.c libiberty/getruntime.c libiberty/hashtab.c libiberty/partition.c libiberty/pexecute.c libiberty/splay-tree.c libiberty/vasprintf.c libiberty/xmalloc.c ltconfig ltmain.sh mkdep opcodes/ChangeLog opcodes/Makefile.am opcodes/Makefile.in opcodes/aclocal.m4 opcodes/alpha-dis.c opcodes/alpha-opc.c opcodes/arm-dis.c opcodes/arm-opc.h opcodes/avr-dis.c opcodes/cgen-opc.c opcodes/configure opcodes/configure.in opcodes/d10v-opc.c opcodes/d30v-dis.c opcodes/d30v-opc.c opcodes/dis-buf.c opcodes/disassemble.c opcodes/fr30-asm.c opcodes/fr30-desc.h opcodes/fr30-dis.c opcodes/fr30-ibld.c opcodes/fr30-opc.c opcodes/hppa-dis.c opcodes/i370-dis.c opcodes/i370-opc.c opcodes/i386-dis.c opcodes/m10300-dis.c opcodes/m10300-opc.c opcodes/m32r-asm.c opcodes/m32r-desc.c opcodes/m32r-desc.h opcodes/m32r-dis.c opcodes/m32r-ibld.c opcodes/m32r-opc.c opcodes/m32r-opc.h opcodes/m32r-opinst.c opcodes/m68k-dis.c opcodes/m68k-opc.c opcodes/mcore-dis.c opcodes/mcore-opc.h opcodes/mips-dis.c opcodes/mips-opc.c opcodes/pj-dis.c opcodes/pj-opc.c opcodes/po/POTFILES.in opcodes/po/opcodes.pot opcodes/ppc-opc.c opcodes/sh-dis.c opcodes/sh-opc.h opcodes/sparc-dis.c opcodes/sparc-opc.c opcodes/tic30-dis.c texinfo/texinfo.tex Delete: bfd/configure.bat bfd/makefile.dos binutils/configure.bat config/mh-aix43 configure.bat gas/config/go32.cfg gas/config/te-multi.h gas/configure.bat gprof/configure.bat include/wait.h intl/ChangeLog.Cygnus ld/configure.bat ld/emulparams/go32.sh ld/emultempl/stringify.sed ld/scripttempl/go32coff.sc ld/testsuite/ld-selective/5.cc libiberty/configure.bat libiberty/makefile.dos makeall.bat opcodes/configure.bat
1066 lines
27 KiB
C
1066 lines
27 KiB
C
/* Instruction printing code for the ARM
|
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Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
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Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Modification by James G. Smith (jsmith@cygnus.co.uk)
|
||
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This file is part of libopcodes.
|
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This program is free software; you can redistribute it and/or modify it under
|
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the terms of the GNU General Public License as published by the Free
|
||
Software Foundation; either version 2 of the License, or (at your option)
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||
any later version.
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||
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||
more details.
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||
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You should have received a copy of the GNU General Public License
|
||
along with this program; if not, write to the Free Software
|
||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#define DEFINE_TABLE
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#include "arm-opc.h"
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#include "coff/internal.h"
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#include "libcoff.h"
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#include "opintl.h"
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/* FIXME: This shouldn't be done here */
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#include "elf-bfd.h"
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#include "elf/internal.h"
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#include "elf/arm.h"
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#ifndef streq
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#endif
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#ifndef strneq
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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#ifndef NUM_ELEM
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#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
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#endif
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static char * arm_conditional[] =
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{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
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||
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typedef struct
|
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{
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const char * name;
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const char * description;
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const char * reg_names[16];
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}
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arm_regname;
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static arm_regname regnames[] =
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{
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{ "raw" , "Select raw register names",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
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{ "std", "Select register names used in ARM's ISA documentation",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
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{ "apcs", "Select register names used in the APCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
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{ "atpcs", "Select register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
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{ "special-atpcs", "Select special register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
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};
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/* Default to standard register name set. */
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static unsigned int regname_selected = 1;
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#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
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#define arm_regnames regnames[regname_selected].reg_names
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|
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static boolean force_thumb = false;
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static char * arm_fp_const[] =
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{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
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|
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static char * arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
|
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|
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/* Forward declarations. */
|
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static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
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static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
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static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
|
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static void parse_disassembler_options PARAMS ((char *));
|
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static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
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int get_arm_regname_num_options (void);
|
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int set_arm_regname_option (int option);
|
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int get_arm_regnames (int option, const char **setname,
|
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const char **setdescription,
|
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const char ***register_names);
|
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|
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/* Functions. */
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int
|
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get_arm_regname_num_options (void)
|
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{
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return NUM_ARM_REGNAMES;
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}
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|
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int
|
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set_arm_regname_option (int option)
|
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{
|
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int old = regname_selected;
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regname_selected = option;
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return old;
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}
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|
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int
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get_arm_regnames (int option, const char **setname,
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const char **setdescription,
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const char ***register_names)
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{
|
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*setname = regnames[option].name;
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*setdescription = regnames[option].description;
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*register_names = regnames[option].reg_names;
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return 16;
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}
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|
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static void
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arm_decode_shift (given, func, stream)
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long given;
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fprintf_ftype func;
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void * stream;
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{
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func (stream, "%s", arm_regnames[given & 0xf]);
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if ((given & 0xff0) != 0)
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{
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if ((given & 0x10) == 0)
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{
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int amount = (given & 0xf80) >> 7;
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int shift = (given & 0x60) >> 5;
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if (amount == 0)
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{
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if (shift == 3)
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{
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func (stream, ", rrx");
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return;
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}
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amount = 32;
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}
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func (stream, ", %s #%d", arm_shift[shift], amount);
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}
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else
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func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
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arm_regnames[(given & 0xf00) >> 8]);
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}
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (always 4 on ARM). */
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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struct disassemble_info * info;
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long given;
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{
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struct arm_opcode * insn;
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void * stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = arm_opcodes; insn->assembler; insn++)
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{
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if ((given & insn->mask) == insn->value)
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{
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char * c;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case '%':
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func (stream, "%%");
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break;
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case 'a':
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if (((given & 0x000f0000) == 0x000f0000)
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&& ((given & 0x02000000) == 0))
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{
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int offset = given & 0xfff;
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func (stream, "[pc");
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if (given & 0x01000000)
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{
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if ((given & 0x00800000) == 0)
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offset = - offset;
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/* pre-indexed */
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func (stream, ", #%x]", offset);
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offset += pc + 8;
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/* Cope with the possibility of write-back
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being used. Probably a very dangerous thing
|
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for the programmer to do, but who are we to
|
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argue ? */
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if (given & 0x00200000)
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func (stream, "!");
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}
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else
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{
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/* Post indexed. */
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func (stream, "], #%x", offset);
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offset = pc + 8; /* ie ignore the offset. */
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}
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func (stream, "\t; ");
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info->print_address_func (offset, info);
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}
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else
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
|
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if ((given & 0x02000000) == 0)
|
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{
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int offset = given & 0xfff;
|
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if (offset)
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func (stream, ", %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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}
|
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else
|
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{
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func (stream, ", %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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}
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else
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{
|
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if ((given & 0x02000000) == 0)
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{
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int offset = given & 0xfff;
|
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if (offset)
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func (stream, "], %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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else
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func (stream, "]");
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}
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else
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{
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func (stream, "], %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
|
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}
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}
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break;
|
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|
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case 's':
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if ((given & 0x004f0000) == 0x004f0000)
|
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{
|
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/* PC relative with immediate offset. */
|
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
|
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|
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if ((given & 0x00800000) == 0)
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offset = -offset;
|
||
|
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func (stream, "[pc, #%x]\t; ", offset);
|
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|
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(*info->print_address_func)
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(offset + pc + 8, info);
|
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}
|
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else
|
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{
|
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func (stream, "[%s",
|
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arm_regnames[(given >> 16) & 0xf]);
|
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if ((given & 0x01000000) != 0)
|
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{
|
||
/* Pre-indexed. */
|
||
if ((given & 0x00400000) == 0x00400000)
|
||
{
|
||
/* Immediate. */
|
||
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
|
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if (offset)
|
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func (stream, ", %s#%d",
|
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(((given & 0x00800000) == 0)
|
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? "-" : ""), offset);
|
||
}
|
||
else
|
||
{
|
||
/* Register. */
|
||
func (stream, ", %s%s",
|
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(((given & 0x00800000) == 0)
|
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? "-" : ""),
|
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arm_regnames[given & 0xf]);
|
||
}
|
||
|
||
func (stream, "]%s",
|
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((given & 0x00200000) != 0) ? "!" : "");
|
||
}
|
||
else
|
||
{
|
||
/* Post-indexed. */
|
||
if ((given & 0x00400000) == 0x00400000)
|
||
{
|
||
/* Immediate. */
|
||
int offset = ((given & 0xf00) >> 4) | (given & 0xf);
|
||
if (offset)
|
||
func (stream, "], %s#%d",
|
||
(((given & 0x00800000) == 0)
|
||
? "-" : ""), offset);
|
||
else
|
||
func (stream, "]");
|
||
}
|
||
else
|
||
{
|
||
/* Register. */
|
||
func (stream, "], %s%s",
|
||
(((given & 0x00800000) == 0)
|
||
? "-" : ""),
|
||
arm_regnames[given & 0xf]);
|
||
}
|
||
}
|
||
}
|
||
break;
|
||
|
||
case 'b':
|
||
(*info->print_address_func)
|
||
(BDISP (given) * 4 + pc + 8, info);
|
||
break;
|
||
|
||
case 'c':
|
||
func (stream, "%s",
|
||
arm_conditional [(given >> 28) & 0xf]);
|
||
break;
|
||
|
||
case 'm':
|
||
{
|
||
int started = 0;
|
||
int reg;
|
||
|
||
func (stream, "{");
|
||
for (reg = 0; reg < 16; reg++)
|
||
if ((given & (1 << reg)) != 0)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
started = 1;
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
func (stream, "}");
|
||
}
|
||
break;
|
||
|
||
case 'o':
|
||
if ((given & 0x02000000) != 0)
|
||
{
|
||
int rotate = (given & 0xf00) >> 7;
|
||
int immed = (given & 0xff);
|
||
immed = (((immed << (32 - rotate))
|
||
| (immed >> rotate)) & 0xffffffff);
|
||
func (stream, "#%d\t; 0x%x", immed, immed);
|
||
}
|
||
else
|
||
arm_decode_shift (given, func, stream);
|
||
break;
|
||
|
||
case 'p':
|
||
if ((given & 0x0000f000) == 0x0000f000)
|
||
func (stream, "p");
|
||
break;
|
||
|
||
case 't':
|
||
if ((given & 0x01200000) == 0x00200000)
|
||
func (stream, "t");
|
||
break;
|
||
|
||
case 'h':
|
||
if ((given & 0x00000020) == 0x00000020)
|
||
func (stream, "h");
|
||
else
|
||
func (stream, "b");
|
||
break;
|
||
|
||
case 'A':
|
||
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
|
||
if ((given & 0x01000000) != 0)
|
||
{
|
||
int offset = given & 0xff;
|
||
if (offset)
|
||
func (stream, ", %s#%d]%s",
|
||
((given & 0x00800000) == 0 ? "-" : ""),
|
||
offset * 4,
|
||
((given & 0x00200000) != 0 ? "!" : ""));
|
||
else
|
||
func (stream, "]");
|
||
}
|
||
else
|
||
{
|
||
int offset = given & 0xff;
|
||
if (offset)
|
||
func (stream, "], %s#%d",
|
||
((given & 0x00800000) == 0 ? "-" : ""),
|
||
offset * 4);
|
||
else
|
||
func (stream, "]");
|
||
}
|
||
break;
|
||
|
||
case 'C':
|
||
switch (given & 0x00090000)
|
||
{
|
||
default:
|
||
func (stream, "_???");
|
||
break;
|
||
case 0x90000:
|
||
func (stream, "_all");
|
||
break;
|
||
case 0x10000:
|
||
func (stream, "_ctl");
|
||
break;
|
||
case 0x80000:
|
||
func (stream, "_flg");
|
||
break;
|
||
}
|
||
break;
|
||
|
||
case 'F':
|
||
switch (given & 0x00408000)
|
||
{
|
||
case 0:
|
||
func (stream, "4");
|
||
break;
|
||
case 0x8000:
|
||
func (stream, "1");
|
||
break;
|
||
case 0x00400000:
|
||
func (stream, "2");
|
||
break;
|
||
default:
|
||
func (stream, "3");
|
||
}
|
||
break;
|
||
|
||
case 'P':
|
||
switch (given & 0x00080080)
|
||
{
|
||
case 0:
|
||
func (stream, "s");
|
||
break;
|
||
case 0x80:
|
||
func (stream, "d");
|
||
break;
|
||
case 0x00080000:
|
||
func (stream, "e");
|
||
break;
|
||
default:
|
||
func (stream, _("<illegal precision>"));
|
||
break;
|
||
}
|
||
break;
|
||
case 'Q':
|
||
switch (given & 0x00408000)
|
||
{
|
||
case 0:
|
||
func (stream, "s");
|
||
break;
|
||
case 0x8000:
|
||
func (stream, "d");
|
||
break;
|
||
case 0x00400000:
|
||
func (stream, "e");
|
||
break;
|
||
default:
|
||
func (stream, "p");
|
||
break;
|
||
}
|
||
break;
|
||
case 'R':
|
||
switch (given & 0x60)
|
||
{
|
||
case 0:
|
||
break;
|
||
case 0x20:
|
||
func (stream, "p");
|
||
break;
|
||
case 0x40:
|
||
func (stream, "m");
|
||
break;
|
||
default:
|
||
func (stream, "z");
|
||
break;
|
||
}
|
||
break;
|
||
|
||
case '0': case '1': case '2': case '3': case '4':
|
||
case '5': case '6': case '7': case '8': case '9':
|
||
{
|
||
int bitstart = *c++ - '0';
|
||
int bitend = 0;
|
||
while (*c >= '0' && *c <= '9')
|
||
bitstart = (bitstart * 10) + *c++ - '0';
|
||
|
||
switch (*c)
|
||
{
|
||
case '-':
|
||
c++;
|
||
|
||
while (*c >= '0' && *c <= '9')
|
||
bitend = (bitend * 10) + *c++ - '0';
|
||
|
||
if (!bitend)
|
||
abort ();
|
||
|
||
switch (*c)
|
||
{
|
||
case 'r':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
case 'd':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%d", reg);
|
||
}
|
||
break;
|
||
case 'x':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "0x%08x", reg);
|
||
|
||
/* Some SWI instructions have special
|
||
meanings. */
|
||
if ((given & 0x0fffffff) == 0x0FF00000)
|
||
func (stream, "\t; IMB");
|
||
else if ((given & 0x0fffffff) == 0x0FF00001)
|
||
func (stream, "\t; IMBRange");
|
||
}
|
||
break;
|
||
case 'X':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%01x", reg & 0xf);
|
||
}
|
||
break;
|
||
case 'f':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
if (reg > 7)
|
||
func (stream, "#%s",
|
||
arm_fp_const[reg & 7]);
|
||
else
|
||
func (stream, "f%d", reg);
|
||
}
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
break;
|
||
|
||
case '`':
|
||
c++;
|
||
if ((given & (1 << bitstart)) == 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
case '\'':
|
||
c++;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
case '?':
|
||
++c;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c++);
|
||
else
|
||
func (stream, "%c", *++c);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
}
|
||
else
|
||
func (stream, "%c", *c);
|
||
}
|
||
return 4;
|
||
}
|
||
}
|
||
abort ();
|
||
}
|
||
|
||
/* Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction. */
|
||
static int
|
||
print_insn_thumb (pc, info, given)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
long given;
|
||
{
|
||
struct thumb_opcode * insn;
|
||
void * stream = info->stream;
|
||
fprintf_ftype func = info->fprintf_func;
|
||
|
||
for (insn = thumb_opcodes; insn->assembler; insn++)
|
||
{
|
||
if ((given & insn->mask) == insn->value)
|
||
{
|
||
char * c = insn->assembler;
|
||
|
||
/* Special processing for Thumb 2 instruction BL sequence: */
|
||
if (!*c) /* Check for empty (not NULL) assembler string. */
|
||
{
|
||
info->bytes_per_chunk = 4;
|
||
info->bytes_per_line = 4;
|
||
|
||
func (stream, "bl\t");
|
||
|
||
info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
|
||
return 4;
|
||
}
|
||
else
|
||
{
|
||
info->bytes_per_chunk = 2;
|
||
info->bytes_per_line = 4;
|
||
|
||
given &= 0xffff;
|
||
|
||
for (; *c; c++)
|
||
{
|
||
if (*c == '%')
|
||
{
|
||
int domaskpc = 0;
|
||
int domasklr = 0;
|
||
|
||
switch (*++c)
|
||
{
|
||
case '%':
|
||
func (stream, "%%");
|
||
break;
|
||
|
||
case 'S':
|
||
{
|
||
long reg;
|
||
|
||
reg = (given >> 3) & 0x7;
|
||
if (given & (1 << 6))
|
||
reg += 8;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
|
||
case 'D':
|
||
{
|
||
long reg;
|
||
|
||
reg = given & 0x7;
|
||
if (given & (1 << 7))
|
||
reg += 8;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
|
||
case 'T':
|
||
func (stream, "%s",
|
||
arm_conditional [(given >> 8) & 0xf]);
|
||
break;
|
||
|
||
case 'N':
|
||
if (given & (1 << 8))
|
||
domasklr = 1;
|
||
/* Fall through. */
|
||
case 'O':
|
||
if (*c == 'O' && (given & (1 << 8)))
|
||
domaskpc = 1;
|
||
/* Fall through. */
|
||
case 'M':
|
||
{
|
||
int started = 0;
|
||
int reg;
|
||
|
||
func (stream, "{");
|
||
|
||
/* It would be nice if we could spot
|
||
ranges, and generate the rS-rE format: */
|
||
for (reg = 0; (reg < 8); reg++)
|
||
if ((given & (1 << reg)) != 0)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
started = 1;
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
|
||
if (domasklr)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
started = 1;
|
||
func (stream, arm_regnames[14] /* "lr" */);
|
||
}
|
||
|
||
if (domaskpc)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
func (stream, arm_regnames[15] /* "pc" */);
|
||
}
|
||
|
||
func (stream, "}");
|
||
}
|
||
break;
|
||
|
||
|
||
case '0': case '1': case '2': case '3': case '4':
|
||
case '5': case '6': case '7': case '8': case '9':
|
||
{
|
||
int bitstart = *c++ - '0';
|
||
int bitend = 0;
|
||
|
||
while (*c >= '0' && *c <= '9')
|
||
bitstart = (bitstart * 10) + *c++ - '0';
|
||
|
||
switch (*c)
|
||
{
|
||
case '-':
|
||
{
|
||
long reg;
|
||
|
||
c++;
|
||
while (*c >= '0' && *c <= '9')
|
||
bitend = (bitend * 10) + *c++ - '0';
|
||
if (!bitend)
|
||
abort ();
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
switch (*c)
|
||
{
|
||
case 'r':
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
break;
|
||
|
||
case 'd':
|
||
func (stream, "%d", reg);
|
||
break;
|
||
|
||
case 'H':
|
||
func (stream, "%d", reg << 1);
|
||
break;
|
||
|
||
case 'W':
|
||
func (stream, "%d", reg << 2);
|
||
break;
|
||
|
||
case 'a':
|
||
/* PC-relative address -- the bottom two
|
||
bits of the address are dropped
|
||
before the calculation. */
|
||
info->print_address_func
|
||
(((pc + 4) & ~3) + (reg << 2), info);
|
||
break;
|
||
|
||
case 'x':
|
||
func (stream, "0x%04x", reg);
|
||
break;
|
||
|
||
case 'I':
|
||
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
||
func (stream, "%d", reg);
|
||
break;
|
||
|
||
case 'B':
|
||
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
||
(*info->print_address_func)
|
||
(reg * 2 + pc + 4, info);
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
break;
|
||
|
||
case '\'':
|
||
c++;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
|
||
case '?':
|
||
++c;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c++);
|
||
else
|
||
func (stream, "%c", *++c);
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
else
|
||
func (stream, "%c", *c);
|
||
}
|
||
}
|
||
return 2;
|
||
}
|
||
}
|
||
|
||
/* No match. */
|
||
abort ();
|
||
}
|
||
|
||
/* Parse an individual disassembler option. */
|
||
void
|
||
parse_arm_disassembler_option (option)
|
||
char * option;
|
||
{
|
||
if (option == NULL)
|
||
return;
|
||
|
||
if (strneq (option, "reg-names-", 10))
|
||
{
|
||
int i;
|
||
|
||
option += 10;
|
||
|
||
for (i = NUM_ARM_REGNAMES; i--;)
|
||
if (streq (option, regnames[i].name))
|
||
{
|
||
regname_selected = i;
|
||
break;
|
||
}
|
||
|
||
if (i < 0)
|
||
fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
|
||
}
|
||
else if (streq (option, "force-thumb"))
|
||
force_thumb = 1;
|
||
else if (streq (option, "no-force-thumb"))
|
||
force_thumb = 0;
|
||
else
|
||
fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
|
||
|
||
return;
|
||
}
|
||
|
||
/* Parse the string of disassembler options, spliting it at whitespaces. */
|
||
static void
|
||
parse_disassembler_options (options)
|
||
char * options;
|
||
{
|
||
char * space;
|
||
|
||
if (options == NULL)
|
||
return;
|
||
|
||
do
|
||
{
|
||
space = strchr (options, ' ');
|
||
|
||
if (space)
|
||
{
|
||
* space = '\0';
|
||
parse_arm_disassembler_option (options);
|
||
* space = ' ';
|
||
options = space + 1;
|
||
}
|
||
else
|
||
parse_arm_disassembler_option (options);
|
||
}
|
||
while (space);
|
||
}
|
||
|
||
/* NOTE: There are no checks in these routines that
|
||
the relevant number of data bytes exist. */
|
||
static int
|
||
print_insn (pc, info, little)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
boolean little;
|
||
{
|
||
unsigned char b[4];
|
||
long given;
|
||
int status;
|
||
int is_thumb;
|
||
|
||
if (info->disassembler_options)
|
||
{
|
||
parse_disassembler_options (info->disassembler_options);
|
||
|
||
/* To avoid repeated parsing of these options, we remove them here. */
|
||
info->disassembler_options = NULL;
|
||
}
|
||
|
||
is_thumb = force_thumb;
|
||
|
||
if (!is_thumb && info->symbols != NULL)
|
||
{
|
||
if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
||
{
|
||
coff_symbol_type * cs;
|
||
|
||
cs = coffsymbol (*info->symbols);
|
||
is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
||
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
||
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
||
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
||
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
||
}
|
||
else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
|
||
{
|
||
elf_symbol_type * es;
|
||
unsigned int type;
|
||
|
||
es = *(elf_symbol_type **)(info->symbols);
|
||
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
||
|
||
is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
|
||
}
|
||
}
|
||
|
||
info->bytes_per_chunk = 4;
|
||
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
|
||
|
||
if (little)
|
||
{
|
||
status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
|
||
if (status != 0 && is_thumb)
|
||
{
|
||
info->bytes_per_chunk = 2;
|
||
|
||
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
||
b[3] = b[2] = 0;
|
||
}
|
||
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
||
}
|
||
else
|
||
{
|
||
status = info->read_memory_func
|
||
(pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
if (is_thumb)
|
||
{
|
||
if (pc & 0x2)
|
||
{
|
||
given = (b[2] << 8) | b[3];
|
||
|
||
status = info->read_memory_func
|
||
((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc + 4, info);
|
||
return -1;
|
||
}
|
||
|
||
given |= (b[0] << 24) | (b[1] << 16);
|
||
}
|
||
else
|
||
given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
|
||
}
|
||
else
|
||
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
|
||
}
|
||
|
||
if (is_thumb)
|
||
status = print_insn_thumb (pc, info, given);
|
||
else
|
||
status = print_insn_arm (pc, info, given);
|
||
|
||
return status;
|
||
}
|
||
|
||
int
|
||
print_insn_big_arm (pc, info)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
{
|
||
return print_insn (pc, info, false);
|
||
}
|
||
|
||
int
|
||
print_insn_little_arm (pc, info)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
{
|
||
return print_insn (pc, info, true);
|
||
}
|
||
|
||
void
|
||
print_arm_disassembler_options (FILE * stream)
|
||
{
|
||
int i;
|
||
|
||
fprintf (stream, _("\n\
|
||
The following ARM specific disassembler options are supported for use with\n\
|
||
the -M switch:\n"));
|
||
|
||
for (i = NUM_ARM_REGNAMES; i--;)
|
||
fprintf (stream, " reg-names-%s %*c%s\n",
|
||
regnames[i].name,
|
||
14 - strlen (regnames[i].name), ' ',
|
||
regnames[i].description);
|
||
|
||
fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
|
||
fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
|
||
}
|