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480 lines
13 KiB
C
480 lines
13 KiB
C
/* Blackfin External Bus Interface Unit (EBIU) Asynchronous Memory Controller
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(AMC) model.
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Copyright (C) 2010-2021 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_ebiu_amc.h"
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struct bfin_ebiu_amc
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{
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bu32 base;
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int type;
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bu32 bank_base, bank_size;
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unsigned (*io_write) (struct hw *, const void *, int, address_word,
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unsigned, struct bfin_ebiu_amc *, bu32, bu32);
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unsigned (*io_read) (struct hw *, void *, int, address_word, unsigned,
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struct bfin_ebiu_amc *, bu32, void *, bu16 *, bu32 *);
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struct hw *slaves[4];
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(amgctl);
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union {
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struct {
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bu32 ambctl0, ambctl1;
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bu32 _pad0[5];
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bu16 BFIN_MMR_16(mode);
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bu16 BFIN_MMR_16(fctl);
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} bf50x;
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struct {
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bu32 ambctl0, ambctl1;
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} bf53x;
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struct {
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bu32 ambctl0, ambctl1;
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bu32 mbsctl, arbstat, mode, fctl;
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} bf54x;
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};
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};
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#define mmr_base() offsetof(struct bfin_ebiu_amc, amgctl)
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#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_amc, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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static const char * const bf50x_mmr_names[] =
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{
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"EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
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[mmr_idx (bf50x.mode)] = "EBIU_MODE", "EBIU_FCTL",
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};
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static const char * const bf53x_mmr_names[] =
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{
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"EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
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};
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static const char * const bf54x_mmr_names[] =
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{
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"EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
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"EBIU_MSBCTL", "EBIU_ARBSTAT", "EBIU_MODE", "EBIU_FCTL",
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};
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static const char * const *mmr_names;
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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static void
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bfin_ebiu_amc_write_amgctl (struct hw *me, struct bfin_ebiu_amc *amc,
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bu16 amgctl)
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{
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bu32 amben_old, amben, addr, i;
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amben_old = min ((amc->amgctl >> 1) & 0x7, 4);
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amben = min ((amgctl >> 1) & 0x7, 4);
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HW_TRACE ((me, "reattaching banks: AMGCTL 0x%04x[%u] -> 0x%04x[%u]",
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amc->amgctl, amben_old, amgctl, amben));
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for (i = 0; i < 4; ++i)
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{
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addr = amc->bank_base + i * amc->bank_size;
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if (i < amben_old)
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{
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HW_TRACE ((me, "detaching bank %u (%#x base)", i, addr));
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sim_core_detach (hw_system (me), NULL, 0, 0, addr);
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}
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if (i < amben)
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{
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struct hw *slave = amc->slaves[i];
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HW_TRACE ((me, "attaching bank %u (%#x base) to %s", i, addr,
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slave ? hw_path (slave) : "<floating pins>"));
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sim_core_attach (hw_system (me), NULL, 0, access_read_write_exec,
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0, addr, amc->bank_size, 0, slave, NULL);
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}
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}
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amc->amgctl = amgctl;
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}
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static unsigned
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bf50x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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bu32 value)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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bfin_ebiu_amc_write_amgctl (me, amc, value);
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break;
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case mmr_offset(bf50x.ambctl0):
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amc->bf50x.ambctl0 = value;
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break;
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case mmr_offset(bf50x.ambctl1):
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amc->bf50x.ambctl1 = value;
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break;
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case mmr_offset(bf50x.mode):
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/* XXX: implement this. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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break;
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case mmr_offset(bf50x.fctl):
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/* XXX: implement this. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bf53x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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bu32 value)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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bfin_ebiu_amc_write_amgctl (me, amc, value);
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break;
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case mmr_offset(bf53x.ambctl0):
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amc->bf53x.ambctl0 = value;
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break;
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case mmr_offset(bf53x.ambctl1):
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amc->bf53x.ambctl1 = value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bf54x_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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bu32 value)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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bfin_ebiu_amc_write_amgctl (me, amc, value);
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break;
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case mmr_offset(bf54x.ambctl0):
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amc->bf54x.ambctl0 = value;
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break;
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case mmr_offset(bf54x.ambctl1):
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amc->bf54x.ambctl1 = value;
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break;
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case mmr_offset(bf54x.mbsctl):
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/* XXX: implement this. */
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break;
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case mmr_offset(bf54x.arbstat):
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/* XXX: implement this. */
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break;
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case mmr_offset(bf54x.mode):
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/* XXX: implement this. */
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break;
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case mmr_offset(bf54x.fctl):
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/* XXX: implement this. */
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_ebiu_amc_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_amc *amc = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_4 (source);
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mmr_off = addr - amc->base;
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HW_TRACE_WRITE ();
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return amc->io_write (me, source, space, addr, nr_bytes,
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amc, mmr_off, value);
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}
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static unsigned
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bf50x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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void *valuep, bu16 *value16, bu32 *value32)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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case mmr_offset(bf50x.fctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16);
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break;
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case mmr_offset(bf50x.ambctl0):
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case mmr_offset(bf50x.ambctl1):
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case mmr_offset(bf50x.mode):
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dv_store_4 (dest, *value32);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bf53x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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void *valuep, bu16 *value16, bu32 *value32)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16);
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break;
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case mmr_offset(bf53x.ambctl0):
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case mmr_offset(bf53x.ambctl1):
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dv_store_4 (dest, *value32);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bf54x_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes,
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struct bfin_ebiu_amc *amc, bu32 mmr_off,
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void *valuep, bu16 *value16, bu32 *value32)
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{
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switch (mmr_off)
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{
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case mmr_offset(amgctl):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16);
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break;
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case mmr_offset(bf54x.ambctl0):
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case mmr_offset(bf54x.ambctl1):
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case mmr_offset(bf54x.mbsctl):
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case mmr_offset(bf54x.arbstat):
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case mmr_offset(bf54x.mode):
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case mmr_offset(bf54x.fctl):
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dv_store_4 (dest, *value32);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_ebiu_amc_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_amc *amc = hw_data (me);
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bu32 mmr_off;
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void *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - amc->base;
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valuep = (void *)((unsigned long)amc + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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return amc->io_read (me, dest, space, addr, nr_bytes, amc,
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mmr_off, valuep, valuep, valuep);
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}
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static void
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bfin_ebiu_amc_attach_address_callback (struct hw *me,
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int level,
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int space,
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address_word addr,
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address_word nr_bytes,
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struct hw *client)
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{
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struct bfin_ebiu_amc *amc = hw_data (me);
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HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s",
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level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client)));
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if (addr + nr_bytes > ARRAY_SIZE (amc->slaves))
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hw_abort (me, "ebiu amc attaches are done in terms of banks");
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while (nr_bytes--)
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amc->slaves[addr + nr_bytes] = client;
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bfin_ebiu_amc_write_amgctl (me, amc, amc->amgctl);
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}
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static void
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attach_bfin_ebiu_amc_regs (struct hw *me, struct bfin_ebiu_amc *amc,
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unsigned reg_size)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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if (hw_find_property (me, "type") == NULL)
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hw_abort (me, "Missing \"type\" property");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != reg_size)
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hw_abort (me, "\"reg\" size must be %#x", reg_size);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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amc->base = attach_address;
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}
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static void
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bfin_ebiu_amc_finish (struct hw *me)
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{
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struct bfin_ebiu_amc *amc;
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bu32 amgctl;
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unsigned reg_size;
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amc = HW_ZALLOC (me, struct bfin_ebiu_amc);
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set_hw_data (me, amc);
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set_hw_io_read_buffer (me, bfin_ebiu_amc_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_ebiu_amc_io_write_buffer);
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set_hw_attach_address (me, bfin_ebiu_amc_attach_address_callback);
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amc->type = hw_find_integer_property (me, "type");
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switch (amc->type)
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{
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case 500 ... 509:
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amc->io_write = bf50x_ebiu_amc_io_write_buffer;
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amc->io_read = bf50x_ebiu_amc_io_read_buffer;
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mmr_names = bf50x_mmr_names;
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reg_size = sizeof (amc->bf50x) + 4;
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/* Initialize the AMC. */
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amc->bank_base = BFIN_EBIU_AMC_BASE;
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amc->bank_size = 1 * 1024 * 1024;
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amgctl = 0x00F3;
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amc->bf50x.ambctl0 = 0x0000FFC2;
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amc->bf50x.ambctl1 = 0x0000FFC2;
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amc->bf50x.mode = 0x0001;
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amc->bf50x.fctl = 0x0002;
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break;
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case 540 ... 549:
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amc->io_write = bf54x_ebiu_amc_io_write_buffer;
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amc->io_read = bf54x_ebiu_amc_io_read_buffer;
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mmr_names = bf54x_mmr_names;
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reg_size = sizeof (amc->bf54x) + 4;
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/* Initialize the AMC. */
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amc->bank_base = BFIN_EBIU_AMC_BASE;
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amc->bank_size = 64 * 1024 * 1024;
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amgctl = 0x0002;
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amc->bf54x.ambctl0 = 0xFFC2FFC2;
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amc->bf54x.ambctl1 = 0xFFC2FFC2;
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amc->bf54x.fctl = 0x0006;
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break;
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case 510 ... 519:
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case 522 ... 527:
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case 531 ... 533:
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case 534:
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case 536:
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case 537:
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case 538 ... 539:
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case 561:
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amc->io_write = bf53x_ebiu_amc_io_write_buffer;
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amc->io_read = bf53x_ebiu_amc_io_read_buffer;
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mmr_names = bf53x_mmr_names;
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reg_size = sizeof (amc->bf53x) + 4;
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/* Initialize the AMC. */
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amc->bank_base = BFIN_EBIU_AMC_BASE;
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if (amc->type == 561)
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amc->bank_size = 64 * 1024 * 1024;
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else
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amc->bank_size = 1 * 1024 * 1024;
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amgctl = 0x00F2;
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amc->bf53x.ambctl0 = 0xFFC2FFC2;
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amc->bf53x.ambctl1 = 0xFFC2FFC2;
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break;
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case 590 ... 599: /* BF59x has no AMC. */
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default:
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hw_abort (me, "no support for EBIU AMC on this Blackfin model yet");
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}
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attach_bfin_ebiu_amc_regs (me, amc, reg_size);
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bfin_ebiu_amc_write_amgctl (me, amc, amgctl);
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}
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const struct hw_descriptor dv_bfin_ebiu_amc_descriptor[] =
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{
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{"bfin_ebiu_amc", bfin_ebiu_amc_finish,},
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{NULL, NULL},
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};
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