binutils-gdb/sim/mips
Frank Ch. Eigler 174ff2242b * R5900 COP2 sim testing in progress. The majority of instructions actually
work!

[ChangeLog.sky]

	* sky-vu.h (vu_device): Represent "macro instruction just stuffed
 	into fetch buffer" condition with new "m" bit.  Rename old "m" to
 	"l".

	* sky-libvpe.c (indebug): Save snapshot of environment value;
 	workaround for suspected memory corruption.
	(fetch_inst): Respect new "m" macro-instruction flag for reporting
 	successful fetch to caller.
	(exec_inst): Disassemble instruction here instead of fetch time.
  	Renamed old "m" -> "l" flag in VU state to track interlock
 	release.
	(vpecallms_cycle): Call exec_inst only if fetch_inst did some
 	work.

	* sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to
 	ensure complete clear of tail part of struct at attach time.
	(vu0_busy): Fix thinko.
	(vu0_macro_issue): Adapt to new "l" flag.
	(vu0_micro_interlock_released): Ditto.
 	(write_vu_special_reg): Ditto.
	(read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly.
  	The other VU status bits are not yet computed.

[ChangeLog]

	* interp.c (decode_coproc): Do not apply superfluous E (end) flag
 	to upper code of generated VU instruction.
1998-04-07 22:47:53 +00:00
..
.Sanitize Re-do load/store operations so that they work for both 32 and 64 bit 1998-04-02 19:35:39 +00:00
ChangeLog * R5900 COP2 sim testing in progress. The majority of instructions actually 1998-04-07 22:47:53 +00:00
config.in
configure aclocal.m4: Don't enable inlining when cross-compiling. 1998-04-05 07:16:54 +00:00
configure.in aclocal.m4: Don't enable inlining when cross-compiling. 1998-04-05 07:16:54 +00:00
gencode.c
interp.c * R5900 COP2 sim testing in progress. The majority of instructions actually 1998-04-07 22:47:53 +00:00
m16.dc
m16.igen
Makefile.in aclocal.m4: Don't enable inlining when cross-compiling. 1998-04-05 07:16:54 +00:00
mdmx.igen
mips.dc
mips.igen * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF 1998-04-05 16:40:03 +00:00
README.Cygnus
sim-main.c aclocal.m4: Don't enable inlining when cross-compiling. 1998-04-05 07:16:54 +00:00
sim-main.h * R5900 COP2 is now ready for testing. Let loose the dogs! 1998-04-07 00:01:31 +00:00
sky-pke.c * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF 1998-04-05 16:40:03 +00:00
sky-pke.h * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF 1998-04-05 16:40:03 +00:00
tconfig.in
tx.igen Re-do load/store operations so that they work for both 32 and 64 bit 1998-04-02 19:35:39 +00:00
vr4320.igen
vr5400.igen

This directory contains two very different simulators:

	o	gencode (old)

		Gencode.c outputs a single monolithic file that is
		#included by interp.c

	o	igen (new)

		The *.igen files are used as inputs to ../igen/igen.
		A number of separate, fairly modula files, are created.

The new simulator has a number of advantages:

	o	builtin support for multi-simming (single simulator
		image supporting a number of different instruction
		set architectures).

	o	Easier maintenance. The input files are not confused
		by an intermixing with the generator code.

gencode continues to exist so that old architectures can be emulated.
*.igen should be used when adding new architectures or adding
instructions to an existing ISA.

Known bugs?

A mips16 simulator cannot be built using igen.  A custom mips16
engine.c needs to be written.

In mips.igen, the semantics for many of the instructions were created
using code generated by gencode.  Those semantic segments could be
greatly simplified.


----

Old README.Cygnus ...

> README.Cygnus
-------------------------------------------------------------------------------

The following are the main reasons for constructing the simulator as a
generator:

1) Avoid large fixed decode source file, with lots of #ifs controlling
   the compilation. i.e. keep the source cleaner, smaller and easier
   to parse.

2) Allow optimum code to be created, without run-time checks on
   instruction types. Ensure that the simulator engine only includes
   code for the architecture being targetted. e.g. This avoids
   run-time checks on ISA conformance, aswell as increasing
   throughput.

3) Allow updates to the instruction sets to be added quickly. Having a
   table means that the information is together, and is easier to
   manipulate. Having the table generate the engine, rather than the
   run-time parse the table gives higher performance at simulation
   time.

4) Keep all the similar simulation code together. i.e. have a single
   place where, for example, the addition code is held. This ensures that
   updates to the simulation are not spread over a large flat source
   file maintained by the developer.

-------------------------------------------------------------------------------

To keep the simulator simple (and to avoid the slight chance of
mis-matched files) the manifests describing an engine, and the
simulator engine itself, are held in the same source file.

This means that the engine must be included twice, with the first pass
controlled by the SIM_MANIFESTS definition.

-------------------------------------------------------------------------------
> EOF README.Cygnus