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390 lines
11 KiB
C
390 lines
11 KiB
C
/* Copyright (C) 2009-2018 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "common-defs.h"
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#include "aarch64-insn.h"
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/* Toggle this file's internal debugging dump. */
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int aarch64_debug = 0;
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/* Extract a signed value from a bit field within an instruction
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encoding.
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INSN is the instruction opcode.
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WIDTH specifies the width of the bit field to extract (in bits).
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OFFSET specifies the least significant bit of the field where bits
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are numbered zero counting from least to most significant. */
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static int32_t
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extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
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{
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unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
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unsigned shift_r = sizeof (int32_t) * 8 - width;
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return ((int32_t) insn << shift_l) >> shift_r;
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}
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/* Determine if specified bits within an instruction opcode matches a
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specific pattern.
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INSN is the instruction opcode.
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MASK specifies the bits within the opcode that are to be tested
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agsinst for a match with PATTERN. */
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static int
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decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
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{
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return (insn & mask) == pattern;
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}
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/* Decode an opcode if it represents an ADR or ADRP instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_ADRP receives the 'op' field from the decoded instruction.
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RD receives the 'rd' field from the decoded instruction.
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OFFSET receives the 'immhi:immlo' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
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unsigned *rd, int32_t *offset)
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{
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/* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */
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/* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */
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if (decode_masked_match (insn, 0x1f000000, 0x10000000))
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{
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uint32_t immlo = (insn >> 29) & 0x3;
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int32_t immhi = extract_signed_bitfield (insn, 19, 5) << 2;
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*is_adrp = (insn >> 31) & 0x1;
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*rd = (insn >> 0) & 0x1f;
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if (*is_adrp)
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{
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/* The ADRP instruction has an offset with a -/+ 4GB range,
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encoded as (immhi:immlo * 4096). */
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*offset = (immhi | immlo) * 4096;
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}
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else
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*offset = (immhi | immlo);
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x %s x%u, #?\n",
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core_addr_to_string_nz (addr), insn,
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*is_adrp ? "adrp" : "adr", *rd);
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents an branch immediate or branch
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and link immediate instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_BL receives the 'op' bit from the decoded instruction.
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OFFSET receives the immediate offset from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
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int32_t *offset)
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{
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/* b 0001 01ii iiii iiii iiii iiii iiii iiii */
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/* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
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if (decode_masked_match (insn, 0x7c000000, 0x14000000))
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{
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*is_bl = (insn >> 31) & 0x1;
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*offset = extract_signed_bitfield (insn, 26, 0) << 2;
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
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core_addr_to_string_nz (addr), insn,
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*is_bl ? "bl" : "b",
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core_addr_to_string_nz (addr + *offset));
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents a conditional branch instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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COND receives the branch condition field from the decoded
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instruction.
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OFFSET receives the immediate offset from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
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int32_t *offset)
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{
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/* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
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if (decode_masked_match (insn, 0xff000010, 0x54000000))
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{
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*cond = (insn >> 0) & 0xf;
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*offset = extract_signed_bitfield (insn, 19, 5) << 2;
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
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core_addr_to_string_nz (addr), insn, *cond,
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core_addr_to_string_nz (addr + *offset));
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents a CBZ or CBNZ instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS64 receives the 'sf' field from the decoded instruction.
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IS_CBNZ receives the 'op' field from the decoded instruction.
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RN receives the 'rn' field from the decoded instruction.
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OFFSET receives the 'imm19' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
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unsigned *rn, int32_t *offset)
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{
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/* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
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/* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
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if (decode_masked_match (insn, 0x7e000000, 0x34000000))
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{
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*rn = (insn >> 0) & 0x1f;
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*is64 = (insn >> 31) & 0x1;
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*is_cbnz = (insn >> 24) & 0x1;
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*offset = extract_signed_bitfield (insn, 19, 5) << 2;
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
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core_addr_to_string_nz (addr), insn,
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*is_cbnz ? "cbnz" : "cbz",
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core_addr_to_string_nz (addr + *offset));
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents a TBZ or TBNZ instruction.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_TBNZ receives the 'op' field from the decoded instruction.
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BIT receives the bit position field from the decoded instruction.
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RT receives 'rt' field from the decoded instruction.
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IMM receives 'imm' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
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unsigned *bit, unsigned *rt, int32_t *imm)
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{
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/* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
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/* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
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if (decode_masked_match (insn, 0x7e000000, 0x36000000))
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{
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*rt = (insn >> 0) & 0x1f;
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*is_tbnz = (insn >> 24) & 0x1;
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*bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
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*imm = extract_signed_bitfield (insn, 14, 5) << 2;
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if (aarch64_debug)
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{
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debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
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core_addr_to_string_nz (addr), insn,
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*is_tbnz ? "tbnz" : "tbz", *rt, *bit,
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core_addr_to_string_nz (addr + *imm));
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}
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return 1;
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}
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return 0;
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}
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/* Decode an opcode if it represents an LDR or LDRSW instruction taking a
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literal offset from the current PC.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_W is set if the instruction is LDRSW.
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IS64 receives size field from the decoded instruction.
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RT receives the 'rt' field from the decoded instruction.
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OFFSET receives the 'imm' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
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int *is64, unsigned *rt, int32_t *offset)
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{
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/* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
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/* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
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if ((insn & 0x3f000000) == 0x18000000)
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{
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*is_w = (insn >> 31) & 0x1;
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if (*is_w)
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{
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/* LDRSW always takes a 64-bit destination registers. */
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*is64 = 1;
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}
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else
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*is64 = (insn >> 30) & 0x1;
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*rt = (insn >> 0) & 0x1f;
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*offset = extract_signed_bitfield (insn, 19, 5) << 2;
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if (aarch64_debug)
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debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
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core_addr_to_string_nz (addr), insn,
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*is_w ? "ldrsw" : "ldr",
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*is64 ? "x" : "w", *rt);
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return 1;
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}
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return 0;
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}
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/* Visit an instruction INSN by VISITOR with all needed information in DATA.
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PC relative instructions need to be handled specifically:
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- B/BL
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- B.COND
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- CBZ/CBNZ
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- TBZ/TBNZ
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- ADR/ADRP
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- LDR/LDRSW (literal) */
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void
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aarch64_relocate_instruction (uint32_t insn,
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const struct aarch64_insn_visitor *visitor,
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struct aarch64_insn_data *data)
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{
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int is_bl;
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int is64;
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int is_sw;
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int is_cbnz;
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int is_tbnz;
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int is_adrp;
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unsigned rn;
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unsigned rt;
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unsigned rd;
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unsigned cond;
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unsigned bit;
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int32_t offset;
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if (aarch64_decode_b (data->insn_addr, insn, &is_bl, &offset))
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visitor->b (is_bl, offset, data);
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else if (aarch64_decode_bcond (data->insn_addr, insn, &cond, &offset))
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visitor->b_cond (cond, offset, data);
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else if (aarch64_decode_cb (data->insn_addr, insn, &is64, &is_cbnz, &rn,
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&offset))
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visitor->cb (offset, is_cbnz, rn, is64, data);
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else if (aarch64_decode_tb (data->insn_addr, insn, &is_tbnz, &bit, &rt,
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&offset))
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visitor->tb (offset, is_tbnz, rt, bit, data);
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else if (aarch64_decode_adr (data->insn_addr, insn, &is_adrp, &rd, &offset))
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visitor->adr (offset, rd, is_adrp, data);
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else if (aarch64_decode_ldr_literal (data->insn_addr, insn, &is_sw, &is64,
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&rt, &offset))
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visitor->ldr_literal (offset, is_sw, rt, is64, data);
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else
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visitor->others (insn, data);
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}
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/* Write a 32-bit unsigned integer INSN info *BUF. Return the number of
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instructions written (aka. 1). */
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int
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aarch64_emit_insn (uint32_t *buf, uint32_t insn)
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{
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*buf = insn;
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return 1;
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}
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/* Helper function emitting a load or store instruction. */
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int
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aarch64_emit_load_store (uint32_t *buf, uint32_t size,
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enum aarch64_opcodes opcode,
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struct aarch64_register rt,
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struct aarch64_register rn,
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struct aarch64_memory_operand operand)
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{
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uint32_t op;
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switch (operand.type)
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{
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case MEMORY_OPERAND_OFFSET:
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{
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op = ENCODE (1, 1, 24);
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return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
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| ENCODE (operand.index >> 3, 12, 10)
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| ENCODE (rn.num, 5, 5)
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| ENCODE (rt.num, 5, 0));
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}
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case MEMORY_OPERAND_POSTINDEX:
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{
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uint32_t post_index = ENCODE (1, 2, 10);
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op = ENCODE (0, 1, 24);
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return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
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| post_index | ENCODE (operand.index, 9, 12)
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| ENCODE (rn.num, 5, 5)
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| ENCODE (rt.num, 5, 0));
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}
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case MEMORY_OPERAND_PREINDEX:
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{
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uint32_t pre_index = ENCODE (3, 2, 10);
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op = ENCODE (0, 1, 24);
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return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
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| pre_index | ENCODE (operand.index, 9, 12)
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| ENCODE (rn.num, 5, 5)
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| ENCODE (rt.num, 5, 0));
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}
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default:
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return 0;
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}
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}
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