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f872fdbb5b
Make use of the default gdbarch methods for gdbarch_unwind_pc, and gdbarch_unwind_sp where possible. I have not tested this change but, by inspecting the code, I believe the default methods are equivalent to the code being deleted. gdb/ChangeLog: * s12z-tdep.c (s12z_unwind_pc): Delete. (s12z_unwind_sp): Delete. (s12z_gdbarch_init): Don't register deleted functions with gdbarch.
585 lines
17 KiB
C
585 lines
17 KiB
C
/* Target-dependent code for the S12Z, for the GDB.
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Copyright (C) 2018-2019 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* Much of this file is shamelessly copied from or1k-tdep.c and others. */
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#include "defs.h"
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#include "arch-utils.h"
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#include "dwarf2-frame.h"
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#include "common/errors.h"
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#include "frame-unwind.h"
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#include "gdbcore.h"
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#include "gdbcmd.h"
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#include "inferior.h"
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#include "opcode/s12z.h"
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#include "trad-frame.h"
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#include "remote.h"
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/* Two of the registers included in S12Z_N_REGISTERS are
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the CCH and CCL "registers" which are just views into
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the CCW register. */
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#define N_PHYSICAL_REGISTERS (S12Z_N_REGISTERS - 2)
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/* A permutation of all the physical registers. Indexing this array
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with an integer from gdb's internal representation will return the
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register enum. */
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static const int reg_perm[N_PHYSICAL_REGISTERS] =
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{
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REG_D0,
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REG_D1,
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REG_D2,
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REG_D3,
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REG_D4,
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REG_D5,
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REG_D6,
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REG_D7,
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REG_X,
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REG_Y,
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REG_S,
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REG_P,
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REG_CCW
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};
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/* The inverse of the above permutation. Indexing this
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array with a register enum (e.g. REG_D2) will return the register
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number in gdb's internal representation. */
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static const int inv_reg_perm[N_PHYSICAL_REGISTERS] =
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{
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2, 3, 4, 5, /* d2, d3, d4, d5 */
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0, 1, /* d0, d1 */
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6, 7, /* d6, d7 */
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8, 9, 10, 11, 12 /* x, y, s, p, ccw */
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};
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/* Return the name of the register REGNUM. */
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static const char *
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s12z_register_name (struct gdbarch *gdbarch, int regnum)
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{
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/* Registers is declared in opcodes/s12z.h. */
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return registers[reg_perm[regnum]].name;
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}
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static CORE_ADDR
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s12z_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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CORE_ADDR start_pc = 0;
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if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
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{
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CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc);
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if (prologue_end != 0)
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return prologue_end;
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}
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warning (_("%s Failed to find end of prologue PC = %08x\n"),
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__FUNCTION__, (unsigned int) pc);
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return pc;
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}
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static struct type *
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s12z_register_type (struct gdbarch *gdbarch, int reg_nr)
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{
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switch (registers[reg_perm[reg_nr]].bytes)
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{
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case 1:
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return builtin_type (gdbarch)->builtin_uint8;
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case 2:
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return builtin_type (gdbarch)->builtin_uint16;
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case 3:
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return builtin_type (gdbarch)->builtin_uint24;
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case 4:
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return builtin_type (gdbarch)->builtin_uint32;
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default:
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return builtin_type (gdbarch)->builtin_uint32;
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}
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return builtin_type (gdbarch)->builtin_int0;
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}
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static int
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s12z_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int num)
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{
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switch (num)
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{
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case 15: return REG_S;
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case 7: return REG_X;
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case 8: return REG_Y;
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case 42: return REG_D0;
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case 43: return REG_D1;
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case 44: return REG_D2;
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case 45: return REG_D3;
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case 46: return REG_D4;
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case 47: return REG_D5;
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case 48: return REG_D6;
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case 49: return REG_D7;
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}
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return -1;
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}
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/* Support functions for frame handling. */
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/* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */
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static int ATTRIBUTE_PRINTF (2, 3)
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s12z_fprintf_disasm (void *stream, const char *format, ...)
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{
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return 0;
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}
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struct disassemble_info
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s12z_disassemble_info (struct gdbarch *gdbarch)
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{
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struct disassemble_info di;
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init_disassemble_info (&di, &null_stream, s12z_fprintf_disasm);
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di.arch = gdbarch_bfd_arch_info (gdbarch)->arch;
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di.mach = gdbarch_bfd_arch_info (gdbarch)->mach;
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di.endian = gdbarch_byte_order (gdbarch);
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di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr,
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unsigned int len, struct disassemble_info *info)
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{
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return target_read_code (memaddr, myaddr, len);
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};
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return di;
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}
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/* Initialize a prologue cache. */
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static struct trad_frame_cache *
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s12z_frame_cache (struct frame_info *this_frame, void **prologue_cache)
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{
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struct trad_frame_cache *info;
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CORE_ADDR this_sp;
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CORE_ADDR this_sp_for_id;
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CORE_ADDR start_addr;
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CORE_ADDR end_addr;
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/* Nothing to do if we already have this info. */
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if (NULL != *prologue_cache)
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return (struct trad_frame_cache *) *prologue_cache;
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/* Get a new prologue cache and populate it with default values. */
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info = trad_frame_cache_zalloc (this_frame);
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*prologue_cache = info;
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/* Find the start address of this function (which is a normal frame, even
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if the next frame is the sentinel frame) and the end of its prologue. */
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CORE_ADDR this_pc = get_frame_pc (this_frame);
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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find_pc_partial_function (this_pc, NULL, &start_addr, NULL);
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/* Get the stack pointer if we have one (if there's no process executing
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yet we won't have a frame. */
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this_sp = (NULL == this_frame) ? 0 :
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get_frame_register_unsigned (this_frame, REG_S);
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/* Return early if GDB couldn't find the function. */
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if (start_addr == 0)
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{
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warning (_("Couldn't find function including address %s SP is %s\n"),
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paddress (gdbarch, this_pc),
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paddress (gdbarch, this_sp));
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/* JPB: 28-Apr-11. This is a temporary patch, to get round GDB
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crashing right at the beginning. Build the frame ID as best we
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can. */
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trad_frame_set_id (info, frame_id_build (this_sp, this_pc));
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return info;
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}
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/* The default frame base of this frame (for ID purposes only - frame
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base is an overloaded term) is its stack pointer. For now we use the
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value of the SP register in this frame. However if the PC is in the
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prologue of this frame, before the SP has been set up, then the value
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will actually be that of the prev frame, and we'll need to adjust it
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later. */
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trad_frame_set_this_base (info, this_sp);
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this_sp_for_id = this_sp;
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/* We should only examine code that is in the prologue. This is all code
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up to (but not including) end_addr. We should only populate the cache
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while the address is up to (but not including) the PC or end_addr,
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whichever is first. */
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end_addr = s12z_skip_prologue (gdbarch, start_addr);
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/* All the following analysis only occurs if we are in the prologue and
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have executed the code. Check we have a sane prologue size, and if
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zero we are frameless and can give up here. */
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if (end_addr < start_addr)
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error (_("end addr %s is less than start addr %s"),
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paddress (gdbarch, end_addr), paddress (gdbarch, start_addr));
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CORE_ADDR addr = start_addr; /* Where we have got to? */
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int frame_size = 0;
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int saved_frame_size = 0;
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while (this_pc > addr)
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{
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struct disassemble_info di = s12z_disassemble_info (gdbarch);
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/* No instruction can be more than 11 bytes long, I think. */
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gdb_byte buf[11];
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int nb = print_insn_s12z (addr, &di);
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gdb_assert (nb <= 11);
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if (0 != target_read_code (addr, buf, nb))
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memory_error (TARGET_XFER_E_IO, addr);
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if (buf[0] == 0x05) /* RTS */
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{
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frame_size = saved_frame_size;
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}
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/* Conditional Branches. If any of these are encountered, then
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it is likely that a RTS will terminate it. So we need to save
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the frame size so it can be restored. */
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else if ( (buf[0] == 0x02) /* BRSET */
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|| (buf[0] == 0x0B) /* DBcc / TBcc */
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|| (buf[0] == 0x03)) /* BRCLR */
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{
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saved_frame_size = frame_size;
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}
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else if (buf[0] == 0x04) /* PUL/ PSH .. */
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{
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bool pull = buf[1] & 0x80;
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int stack_adjustment = 0;
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if (buf[1] & 0x40)
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{
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if (buf[1] & 0x01) stack_adjustment += 3; /* Y */
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if (buf[1] & 0x02) stack_adjustment += 3; /* X */
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if (buf[1] & 0x04) stack_adjustment += 4; /* D7 */
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if (buf[1] & 0x08) stack_adjustment += 4; /* D6 */
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if (buf[1] & 0x10) stack_adjustment += 2; /* D5 */
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if (buf[1] & 0x20) stack_adjustment += 2; /* D4 */
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}
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else
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{
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if (buf[1] & 0x01) stack_adjustment += 2; /* D3 */
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if (buf[1] & 0x02) stack_adjustment += 2; /* D2 */
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if (buf[1] & 0x04) stack_adjustment += 1; /* D1 */
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if (buf[1] & 0x08) stack_adjustment += 1; /* D0 */
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if (buf[1] & 0x10) stack_adjustment += 1; /* CCL */
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if (buf[1] & 0x20) stack_adjustment += 1; /* CCH */
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}
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if (!pull)
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stack_adjustment = -stack_adjustment;
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frame_size -= stack_adjustment;
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}
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else if (buf[0] == 0x0a) /* LEA S, (xxx, S) */
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{
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if (0x06 == (buf[1] >> 4))
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{
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int simm = (signed char) (buf[1] & 0x0F);
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frame_size -= simm;
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}
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}
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else if (buf[0] == 0x1a) /* LEA S, (S, xxxx) */
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{
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int simm = (signed char) buf[1];
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frame_size -= simm;
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}
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addr += nb;
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}
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/* If the PC has not actually got to this point, then the frame
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base will be wrong, and we adjust it. */
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if (this_pc < addr)
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{
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/* Only do if executing. */
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if (0 != this_sp)
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{
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this_sp_for_id = this_sp - frame_size;
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trad_frame_set_this_base (info, this_sp_for_id);
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}
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trad_frame_set_reg_value (info, REG_S, this_sp + 3);
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trad_frame_set_reg_addr (info, REG_P, this_sp);
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}
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else
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{
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gdb_assert (this_sp == this_sp_for_id);
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/* The stack pointer of the prev frame is frame_size greater
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than the stack pointer of this frame plus one address
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size (caused by the JSR or BSR). */
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trad_frame_set_reg_value (info, REG_S,
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this_sp + frame_size + 3);
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trad_frame_set_reg_addr (info, REG_P, this_sp + frame_size);
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}
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/* Build the frame ID. */
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trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr));
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return info;
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}
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/* Implement the this_id function for the stub unwinder. */
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static void
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s12z_frame_this_id (struct frame_info *this_frame,
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void **prologue_cache, struct frame_id *this_id)
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{
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struct trad_frame_cache *info = s12z_frame_cache (this_frame,
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prologue_cache);
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trad_frame_get_id (info, this_id);
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}
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/* Implement the prev_register function for the stub unwinder. */
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static struct value *
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s12z_frame_prev_register (struct frame_info *this_frame,
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void **prologue_cache, int regnum)
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{
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struct trad_frame_cache *info = s12z_frame_cache (this_frame,
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prologue_cache);
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return trad_frame_get_register (info, this_frame, regnum);
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}
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/* Data structures for the normal prologue-analysis-based unwinder. */
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static const struct frame_unwind s12z_frame_unwind = {
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NORMAL_FRAME,
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default_frame_unwind_stop_reason,
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s12z_frame_this_id,
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s12z_frame_prev_register,
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NULL,
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default_frame_sniffer,
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NULL,
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};
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constexpr gdb_byte s12z_break_insn[] = {0x00};
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typedef BP_MANIPULATION (s12z_break_insn) s12z_breakpoint;
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struct gdbarch_tdep
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{
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};
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/* A vector of human readable characters representing the
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bits in the CCW register. Unused bits are represented as '-'.
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Lowest significant bit comes first. */
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static const char ccw_bits[] =
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{
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'C', /* Carry */
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'V', /* Two's Complement Overflow */
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'Z', /* Zero */
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'N', /* Negative */
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'I', /* Interrupt */
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'-',
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'X', /* Non-Maskable Interrupt */
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'S', /* STOP Disable */
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'0', /* Interrupt priority level */
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'0', /* ditto */
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'0', /* ditto */
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'-',
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'-',
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'-',
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'-',
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'U' /* User/Supervisor State. */
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};
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/* Print a human readable representation of the CCW register.
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For example: "u----000SX-Inzvc" corresponds to the value
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0xD0. */
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static void
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s12z_print_ccw_info (struct gdbarch *gdbarch,
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struct ui_file *file,
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struct frame_info *frame,
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int reg)
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{
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struct value *v = value_of_register (reg, frame);
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const char *name = gdbarch_register_name (gdbarch, reg);
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uint32_t ccw = value_as_long (v);
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fputs_filtered (name, file);
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size_t len = strlen (name);
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const int stop_1 = 15;
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const int stop_2 = 17;
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for (int i = 0; i < stop_1 - len; ++i)
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fputc_filtered (' ', file);
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fprintf_filtered (file, "0x%04x", ccw);
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for (int i = 0; i < stop_2 - len; ++i)
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fputc_filtered (' ', file);
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for (int b = 15; b >= 0; --b)
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{
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if (ccw & (0x1u << b))
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{
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if (ccw_bits[b] == 0)
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fputc_filtered ('1', file);
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else
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fputc_filtered (ccw_bits[b], file);
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}
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else
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fputc_filtered (tolower (ccw_bits[b]), file);
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}
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fputc_filtered ('\n', file);
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}
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static void
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s12z_print_registers_info (struct gdbarch *gdbarch,
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struct ui_file *file,
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struct frame_info *frame,
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int regnum, int print_all)
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{
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const int numregs = (gdbarch_num_regs (gdbarch)
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+ gdbarch_num_pseudo_regs (gdbarch));
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if (regnum == -1)
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{
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for (int reg = 0; reg < numregs; reg++)
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{
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if (REG_CCW == reg_perm[reg])
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{
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s12z_print_ccw_info (gdbarch, file, frame, reg);
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continue;
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}
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default_print_registers_info (gdbarch, file, frame, reg, print_all);
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}
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}
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else if (REG_CCW == reg_perm[regnum])
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s12z_print_ccw_info (gdbarch, file, frame, regnum);
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else
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default_print_registers_info (gdbarch, file, frame, regnum, print_all);
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}
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static void
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s12z_extract_return_value (struct type *type, struct regcache *regcache,
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void *valbuf)
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{
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int reg = -1;
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switch (TYPE_LENGTH (type))
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{
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case 0: /* Nothing to do */
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return;
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case 1:
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reg = REG_D0;
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break;
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case 2:
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reg = REG_D2;
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break;
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case 3:
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reg = REG_X;
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break;
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case 4:
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reg = REG_D6;
|
||
break;
|
||
|
||
default:
|
||
error (_("bad size for return value"));
|
||
return;
|
||
}
|
||
|
||
regcache->cooked_read (inv_reg_perm[reg], (gdb_byte *) valbuf);
|
||
}
|
||
|
||
static enum return_value_convention
|
||
s12z_return_value (struct gdbarch *gdbarch, struct value *function,
|
||
struct type *type, struct regcache *regcache,
|
||
gdb_byte *readbuf, const gdb_byte *writebuf)
|
||
{
|
||
if (TYPE_CODE (type) == TYPE_CODE_STRUCT
|
||
|| TYPE_CODE (type) == TYPE_CODE_UNION
|
||
|| TYPE_CODE (type) == TYPE_CODE_ARRAY
|
||
|| TYPE_LENGTH (type) > 4)
|
||
return RETURN_VALUE_STRUCT_CONVENTION;
|
||
|
||
if (readbuf)
|
||
s12z_extract_return_value (type, regcache, readbuf);
|
||
|
||
return RETURN_VALUE_REGISTER_CONVENTION;
|
||
}
|
||
|
||
|
||
static void
|
||
show_bdccsr_command (const char *args, int from_tty)
|
||
{
|
||
struct string_file output;
|
||
target_rcmd ("bdccsr", &output);
|
||
|
||
printf_unfiltered ("The current BDCCSR value is %s\n", output.string().c_str());
|
||
}
|
||
|
||
static struct gdbarch *
|
||
s12z_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
||
{
|
||
struct gdbarch_tdep *tdep = XNEW (struct gdbarch_tdep);
|
||
struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
|
||
|
||
add_cmd ("bdccsr", class_support, show_bdccsr_command,
|
||
_("Show the current value of the microcontroller's BDCCSR."),
|
||
&maintenanceinfolist);
|
||
|
||
/* Target data types. */
|
||
set_gdbarch_short_bit (gdbarch, 16);
|
||
set_gdbarch_int_bit (gdbarch, 16);
|
||
set_gdbarch_long_bit (gdbarch, 32);
|
||
set_gdbarch_long_long_bit (gdbarch, 32);
|
||
set_gdbarch_ptr_bit (gdbarch, 24);
|
||
set_gdbarch_addr_bit (gdbarch, 24);
|
||
set_gdbarch_char_signed (gdbarch, 0);
|
||
|
||
set_gdbarch_ps_regnum (gdbarch, REG_CCW);
|
||
set_gdbarch_pc_regnum (gdbarch, REG_P);
|
||
set_gdbarch_sp_regnum (gdbarch, REG_S);
|
||
|
||
|
||
set_gdbarch_print_registers_info (gdbarch, s12z_print_registers_info);
|
||
|
||
set_gdbarch_breakpoint_kind_from_pc (gdbarch,
|
||
s12z_breakpoint::kind_from_pc);
|
||
set_gdbarch_sw_breakpoint_from_kind (gdbarch,
|
||
s12z_breakpoint::bp_from_kind);
|
||
|
||
set_gdbarch_num_regs (gdbarch, N_PHYSICAL_REGISTERS);
|
||
set_gdbarch_register_name (gdbarch, s12z_register_name);
|
||
set_gdbarch_skip_prologue (gdbarch, s12z_skip_prologue);
|
||
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
|
||
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, s12z_dwarf_reg_to_regnum);
|
||
|
||
set_gdbarch_register_type (gdbarch, s12z_register_type);
|
||
|
||
frame_unwind_append_unwinder (gdbarch, &s12z_frame_unwind);
|
||
/* Currently, the only known producer for this archtecture, produces buggy
|
||
dwarf CFI. So don't append a dwarf unwinder until the situation is
|
||
better understood. */
|
||
|
||
set_gdbarch_return_value (gdbarch, s12z_return_value);
|
||
|
||
return gdbarch;
|
||
}
|
||
|
||
void
|
||
_initialize_s12z_tdep (void)
|
||
{
|
||
gdbarch_register (bfd_arch_s12z, s12z_gdbarch_init, NULL);
|
||
}
|