mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-15 04:31:49 +08:00
3cc17af589
Now that the opcode table gets preprocessed, undo parts of commit
dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the
preprocessor handle the expansion there, while making the expansions
explicit in i386-gen and the register table.
322 lines
13 KiB
Plaintext
322 lines
13 KiB
Plaintext
// i386 register table.
|
|
// Copyright (C) 2007-2019 Free Software Foundation, Inc.
|
|
//
|
|
// This file is part of the GNU opcodes library.
|
|
//
|
|
// This library is free software; you can redistribute it and/or modify
|
|
// it under the terms of the GNU General Public License as published by
|
|
// the Free Software Foundation; either version 3, or (at your option)
|
|
// any later version.
|
|
//
|
|
// It is distributed in the hope that it will be useful, but WITHOUT
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
// License for more details.
|
|
//
|
|
// You should have received a copy of the GNU General Public License
|
|
// along with GAS; see the file COPYING. If not, write to the Free
|
|
// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
|
// 02110-1301, USA.
|
|
|
|
// Make %st first as we test for it.
|
|
st, Reg|Acc|Tbyte, 0, 0, 11, 33
|
|
// 8 bit regs
|
|
al, Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
|
|
cl, Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
|
|
dl, Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
|
|
bl, Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
|
|
ah, Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
|
|
ch, Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
|
|
dh, Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
|
|
bh, Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
|
|
axl, Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
|
|
cxl, Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
|
|
dxl, Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
|
|
bxl, Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
|
|
spl, Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
|
|
bpl, Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
|
|
sil, Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
|
|
dil, Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
|
|
r8b, Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
|
|
r9b, Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
|
|
r10b, Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
|
|
r11b, Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
|
|
r12b, Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
|
|
r13b, Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
|
|
r14b, Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
|
|
r15b, Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
|
|
// 16 bit regs
|
|
ax, Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
|
|
cx, Reg|Word, 0, 1, Dw2Inval, Dw2Inval
|
|
dx, Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
|
|
bx, Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
|
|
sp, Reg|Word, 0, 4, Dw2Inval, Dw2Inval
|
|
bp, Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
|
|
si, Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
|
|
di, Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
|
|
r8w, Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
|
|
r9w, Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
|
|
r10w, Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
|
|
r11w, Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
|
|
r12w, Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
|
|
r13w, Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
|
|
r14w, Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
|
|
r15w, Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
|
|
// 32 bit regs
|
|
eax, Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
|
|
ecx, Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
|
|
edx, Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
|
|
ebx, Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
|
|
esp, Reg|Dword, 0, 4, 4, Dw2Inval
|
|
ebp, Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
|
|
esi, Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
|
|
edi, Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
|
|
r8d, Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
|
|
r9d, Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
|
|
r10d, Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
|
|
r11d, Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
|
|
r12d, Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
|
|
r13d, Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
|
|
r14d, Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
|
|
r15d, Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
|
|
rax, Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
|
|
rcx, Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
|
|
rdx, Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
|
|
rbx, Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
|
|
rsp, Reg|Qword, 0, 4, Dw2Inval, 7
|
|
rbp, Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
|
|
rsi, Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
|
|
rdi, Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
|
|
r8, Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
|
|
r9, Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
|
|
r10, Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
|
|
r11, Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
|
|
r12, Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
|
|
r13, Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
|
|
r14, Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
|
|
r15, Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
|
|
// Vector mask registers.
|
|
k0, RegMask, 0, 0, 93, 118
|
|
k1, RegMask, 0, 1, 94, 119
|
|
k2, RegMask, 0, 2, 95, 120
|
|
k3, RegMask, 0, 3, 96, 121
|
|
k4, RegMask, 0, 4, 97, 122
|
|
k5, RegMask, 0, 5, 98, 123
|
|
k6, RegMask, 0, 6, 99, 124
|
|
k7, RegMask, 0, 7, 100, 125
|
|
// Segment registers.
|
|
es, SReg, 0, 0, 40, 50
|
|
cs, SReg, 0, 1, 41, 51
|
|
ss, SReg, 0, 2, 42, 52
|
|
ds, SReg, 0, 3, 43, 53
|
|
fs, SReg, 0, 4, 44, 54
|
|
gs, SReg, 0, 5, 45, 55
|
|
flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
|
|
// Control registers.
|
|
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
|
|
cr1, Control, 0, 1, Dw2Inval, Dw2Inval
|
|
cr2, Control, 0, 2, Dw2Inval, Dw2Inval
|
|
cr3, Control, 0, 3, Dw2Inval, Dw2Inval
|
|
cr4, Control, 0, 4, Dw2Inval, Dw2Inval
|
|
cr5, Control, 0, 5, Dw2Inval, Dw2Inval
|
|
cr6, Control, 0, 6, Dw2Inval, Dw2Inval
|
|
cr7, Control, 0, 7, Dw2Inval, Dw2Inval
|
|
cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
|
|
cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
|
|
cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
|
|
cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
|
|
cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
|
|
cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
|
|
cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
|
|
cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
|
|
// Debug registers.
|
|
db0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
|
db1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
|
db2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
|
db3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
|
db4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
|
db5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
|
db6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
|
db7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
|
db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
|
db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
|
db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
|
db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
|
db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
|
db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
|
db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
|
db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
|
dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
|
dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
|
dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
|
dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
|
dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
|
dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
|
dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
|
dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
|
dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
|
dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
|
dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
|
dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
|
dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
|
dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
|
dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
|
dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
|
// Test registers.
|
|
tr0, Test, 0, 0, Dw2Inval, Dw2Inval
|
|
tr1, Test, 0, 1, Dw2Inval, Dw2Inval
|
|
tr2, Test, 0, 2, Dw2Inval, Dw2Inval
|
|
tr3, Test, 0, 3, Dw2Inval, Dw2Inval
|
|
tr4, Test, 0, 4, Dw2Inval, Dw2Inval
|
|
tr5, Test, 0, 5, Dw2Inval, Dw2Inval
|
|
tr6, Test, 0, 6, Dw2Inval, Dw2Inval
|
|
tr7, Test, 0, 7, Dw2Inval, Dw2Inval
|
|
// MMX and simd registers.
|
|
mm0, RegMMX, 0, 0, 29, 41
|
|
mm1, RegMMX, 0, 1, 30, 42
|
|
mm2, RegMMX, 0, 2, 31, 43
|
|
mm3, RegMMX, 0, 3, 32, 44
|
|
mm4, RegMMX, 0, 4, 33, 45
|
|
mm5, RegMMX, 0, 5, 34, 46
|
|
mm6, RegMMX, 0, 6, 35, 47
|
|
mm7, RegMMX, 0, 7, 36, 48
|
|
xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17
|
|
xmm1, RegSIMD|Xmmword, 0, 1, 22, 18
|
|
xmm2, RegSIMD|Xmmword, 0, 2, 23, 19
|
|
xmm3, RegSIMD|Xmmword, 0, 3, 24, 20
|
|
xmm4, RegSIMD|Xmmword, 0, 4, 25, 21
|
|
xmm5, RegSIMD|Xmmword, 0, 5, 26, 22
|
|
xmm6, RegSIMD|Xmmword, 0, 6, 27, 23
|
|
xmm7, RegSIMD|Xmmword, 0, 7, 28, 24
|
|
xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
|
|
xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
|
|
xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
|
|
xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
|
|
xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
|
|
xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
|
|
xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
|
|
xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
|
|
xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
|
|
xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
|
|
xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
|
|
xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
|
|
xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
|
|
xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
|
|
xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
|
|
xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
|
|
xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
|
|
xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
|
|
xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
|
|
xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
|
|
xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
|
|
xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
|
|
xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
|
|
xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
|
|
// AVX registers.
|
|
ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
|
|
ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
|
|
ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
|
|
ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
|
|
ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
|
|
ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
|
|
ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
|
|
ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
|
|
ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
|
|
ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
|
|
ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
|
|
ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
|
|
ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
|
|
ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
|
|
ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
|
|
ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
|
|
ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
|
|
ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
|
ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
|
ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
|
ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
|
ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
|
ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
|
ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
|
ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
|
ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
|
ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
|
ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
|
ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
|
ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
|
ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
|
ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
|
// AVX512 registers.
|
|
zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
|
|
zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
|
|
zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
|
|
zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
|
|
zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
|
|
zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
|
|
zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
|
|
zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
|
|
zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
|
|
zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
|
|
zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
|
|
zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
|
|
zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
|
|
zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
|
|
zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
|
|
zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
|
|
zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
|
|
zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
|
|
zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
|
|
zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
|
|
zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
|
|
zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
|
|
zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
|
|
zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
|
|
zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
|
zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
|
zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
|
zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
|
zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
|
zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
|
zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
|
zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
|
// Bound registers for MPX
|
|
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
|
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
|
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
|
|
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
|
|
// No Reg will make these registers rejected for all purposes except
|
|
// for addressing. This saves creating one extra type for RIP/EIP.
|
|
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
|
|
eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
|
// No Reg will make these registers rejected for all purposes except
|
|
// for addressing.
|
|
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
|
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
|
// fp regs.
|
|
st(0), Reg|Acc|Tbyte, 0, 0, 11, 33
|
|
st(1), Reg|Tbyte, 0, 1, 12, 34
|
|
st(2), Reg|Tbyte, 0, 2, 13, 35
|
|
st(3), Reg|Tbyte, 0, 3, 14, 36
|
|
st(4), Reg|Tbyte, 0, 4, 15, 37
|
|
st(5), Reg|Tbyte, 0, 5, 16, 38
|
|
st(6), Reg|Tbyte, 0, 6, 17, 39
|
|
st(7), Reg|Tbyte, 0, 7, 18, 40
|
|
// Pseudo-register names only used in .cfi_* directives
|
|
eflags, 0, 0, 0, 9, 49
|
|
rflags, 0, 0, 0, Dw2Inval, 49
|
|
fs.base, 0, 0, 0, Dw2Inval, 58
|
|
gs.base, 0, 0, 0, Dw2Inval, 59
|
|
tr, 0, 0, 0, 48, 62
|
|
ldtr, 0, 0, 0, 49, 63
|
|
// st0...7 for backward compatibility
|
|
st0, 0, 0, 0, 11, 33
|
|
st1, 0, 0, 1, 12, 34
|
|
st2, 0, 0, 2, 13, 35
|
|
st3, 0, 0, 3, 14, 36
|
|
st4, 0, 0, 4, 15, 37
|
|
st5, 0, 0, 5, 16, 38
|
|
st6, 0, 0, 6, 17, 39
|
|
st7, 0, 0, 7, 18, 40
|
|
fcw, 0, 0, 0, 37, 65
|
|
fsw, 0, 0, 0, 38, 66
|
|
mxcsr, 0, 0, 0, 39, 64
|