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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
1011 lines
22 KiB
ArmAsm
1011 lines
22 KiB
ArmAsm
# Hitachi H8 testcase 'subx'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# subx.b #xx:8, rd8 ; b rd8 xxxxxxxx
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# subx.b #xx:8, @erd ; 7 d erd ???? b ???? xxxxxxxx
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# subx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? b ???? xxxxxxxx
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# subx.b rs8, rd8 ; 1 e rs8 rd8
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# subx.b rs8, @erd ; 7 d erd ???? 1 e rs8 ????
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# subx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 1 e rs8 ????
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# subx.b @ers, rd8 ; 7 c ers ???? 1 e ???? rd8
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# subx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 1 e ???? rd8
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# subx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 3 ????
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# subx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 3 ????
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#
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# word ops
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# long ops
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.data
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byte_src: .byte 0x5
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byte_dest: .byte 0
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.align 2
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word_src: .word 0x505
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word_dest: .word 0
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.align 4
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long_src: .long 0x50505
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long_dest: .long 0
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start
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subx_b_imm8_0:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; subx.b #xx:8,Rd ; Subx with carry initially zero.
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subx.b #5, r0l ; Immediate 8-bit operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_b_imm8_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; subx.b #xx:8,Rd ; Subx with carry initially one.
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set_carry_flag
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subx.b #4, r0l ; Immediate 8-bit operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0xa5a0 r0 ; sub result: a5 - (4 + 1)
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - (4 + 1)
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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subx_b_imm8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b #xx:8,@eRd ; Subx to register indirect
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mov #byte_dest, er0
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mov.b #0xa5, @er0
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set_ccr_zero
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subx.b #5, @er0
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 still contains subress
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb1
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fail
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.Lb1:
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subx_b_imm8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b #xx:8,@eRd- ; Subx to register post-decrement
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mov #byte_dest, er0
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mov.b #0xa5, @er0
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set_ccr_zero
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subx.b #5, @er0-
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb2
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fail
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.Lb2:
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.endif
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subx_b_reg8_0:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b Rs,Rd ; subx with carry initially zero
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mov.b #5, r0h
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set_ccr_zero
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subx.b r0h, r0l ; Register operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_b_reg8_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b Rs,Rd ; subx with carry initially one
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mov.b #4, r0h
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set_ccr_zero
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set_carry_flag
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subx.b r0h, r0l ; Register operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0x04a0 r0 ; sub result: a5 - (4 + 1)
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a504a0 er0 ; sub result: a5 - (4 + 1)
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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subx_b_reg8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b rs8,@eRd ; Subx to register indirect
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mov #byte_dest, er0
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mov.b #0xa5, @er0
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mov.b #5, r1l
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set_ccr_zero
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subx.b r1l, @er0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 still contains subress
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb3
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fail
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.Lb3:
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subx_b_reg8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b rs8,@eRd- ; Subx to register post-decrement
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mov #byte_dest, er0
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mov.b #0xa5, @er0
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mov.b #5, r1l
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set_ccr_zero
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subx.b r1l, @er0-
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest-1 er0 ; er0 contains subress minus one
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test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb4
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fail
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.Lb4:
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subx_b_rsind_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b @eRs,rd8 ; Subx from reg indirect to reg
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mov #byte_src, er0
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set_ccr_zero
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subx.b @er0, r1l
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_src er0 ; er0 still contains subress
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test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_b_rspostdec_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b @eRs-,rd8 ; Subx to register post-decrement
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mov #byte_src, er0
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set_ccr_zero
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subx.b @er0-, r1l
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_src-1 er0 ; er0 contains subress minus one
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test_h_gr32 0xa5a5a5a0 er1 ; er1 contains the sum
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_b_rsind_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.b @eRs,rd8 ; Subx from reg indirect to reg
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mov #byte_src, er0
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mov #byte_dest, er1
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mov.b #0xa5, @er1
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set_ccr_zero
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subx.b @er0, @er1
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_src er0 ; er0 still contains src subress
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test_h_gr32 byte_dest er1 ; er1 still contains dst subress
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb5
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fail
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.Lb5:
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subx_b_rspostdec_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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mov #byte_src, er0
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mov #byte_dest, er1
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mov.b #0xa5, @er1
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set_ccr_zero
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;; subx.b @eRs-,@erd- ; Subx post-decrement to post-decrement
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subx.b @er0-, @er1-
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_src-1 er0 ; er0 contains src subress minus one
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test_h_gr32 byte_dest-1 er1 ; er1 contains dst subress minus one
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.b #0xa0, @byte_dest
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beq .Lb6
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fail
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.Lb6:
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subx_w_imm16_0:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; subx.w #xx:16,Rd ; Subx with carry initially zero.
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subx.w #0x505, r0 ; Immediate 16-bit operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505
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test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_w_imm16_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; subx.w #xx:16,Rd ; Subx with carry initially one.
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set_carry_flag
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subx.w #0x504, r0 ; Immediate 16-bit operand
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr16 0xa0a0 r0 ; sub result: 0xa5a5 + 0x505 + 1
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test_h_gr32 0xa5a5a0a0 er0 ; sub result: 0xa5a5 + 0x505 + 1
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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subx_w_imm16_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.w #xx:16,@eRd ; Subx to register indirect
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mov #word_dest, er0
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mov.w #0xa5a5, @er0
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set_ccr_zero
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subx.w #0x505, @er0
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 word_dest er0 ; er0 still contains subress
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the sub to memory.
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cmp.w #0xa0a0, @word_dest
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beq .Lw1
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fail
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.Lw1:
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subx_w_imm16_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; subx.w #xx:16,@eRd- ; Subx to register post-decrement
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mov #word_dest, er0
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mov.w #0xa5a5, @er0
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set_ccr_zero
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subx.w #0x505, @er0-
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.w #0xa0a0, @word_dest
|
|
beq .Lw2
|
|
fail
|
|
.Lw2:
|
|
|
|
subx_w_reg16_0:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w Rs,Rd ; subx with carry initially zero
|
|
mov.w #0x505, e0
|
|
set_ccr_zero
|
|
subx.w e0, r0 ; Register operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0x0505a0a0 er0 ; sub result:
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_w_reg16_1:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w Rs,Rd ; subx with carry initially one
|
|
mov.w #0x504, e0
|
|
set_ccr_zero
|
|
set_carry_flag
|
|
subx.w e0, r0 ; Register operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0x0504a0a0 er0 ; sub result:
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_w_reg16_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w rs8,@eRd ; Subx to register indirect
|
|
mov #word_dest, er0
|
|
mov.w #0xa5a5, @er0
|
|
mov.w #0x505, r1
|
|
set_ccr_zero
|
|
subx.w r1, @er0
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_dest er0 ; er0 still contains subress
|
|
test_h_gr32 0xa5a50505 er1 ; er1 has the test load
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.w #0xa0a0, @word_dest
|
|
beq .Lw3
|
|
fail
|
|
.Lw3:
|
|
|
|
subx_w_reg16_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w rs8,@eRd- ; Subx to register post-decrement
|
|
mov #word_dest, er0
|
|
mov.w #0xa5a5, @er0
|
|
mov.w #0x505, r1
|
|
set_ccr_zero
|
|
subx.w r1, @er0-
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_dest-2 er0 ; er0 contains subress minus one
|
|
test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.w #0xa0a0, @word_dest
|
|
beq .Lw4
|
|
fail
|
|
.Lw4:
|
|
|
|
subx_w_rsind_reg16:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w @eRs,rd8 ; Subx from reg indirect to reg
|
|
mov #word_src, er0
|
|
set_ccr_zero
|
|
subx.w @er0, r1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_src er0 ; er0 still contains subress
|
|
test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_w_rspostdec_reg16:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w @eRs-,rd8 ; Subx to register post-decrement
|
|
mov #word_src, er0
|
|
set_ccr_zero
|
|
subx.w @er0-, r1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_src-2 er0 ; er0 contains subress minus one
|
|
test_h_gr32 0xa5a5a0a0 er1 ; er1 contains the sum
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_w_rsind_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w @eRs,rd8 ; Subx from reg indirect to reg
|
|
mov #word_src, er0
|
|
mov #word_dest, er1
|
|
mov.w #0xa5a5, @er1
|
|
set_ccr_zero
|
|
subx.w @er0, @er1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_src er0 ; er0 still contains src subress
|
|
test_h_gr32 word_dest er1 ; er1 still contains dst subress
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
;; Now check the result of the sub to memory.
|
|
cmp.w #0xa0a0, @word_dest
|
|
beq .Lw5
|
|
fail
|
|
.Lw5:
|
|
|
|
subx_w_rspostdec_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.w @eRs-,rd8 ; Subx to register post-decrement
|
|
mov #word_src, er0
|
|
mov #word_dest, er1
|
|
mov.w #0xa5a5, @er1
|
|
set_ccr_zero
|
|
subx.w @er0-, @er1-
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 word_src-2 er0 ; er0 contains src subress minus one
|
|
test_h_gr32 word_dest-2 er1 ; er1 contains dst subress minus one
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
;; Now check the result of the sub to memory.
|
|
cmp.w #0xa0a0, @word_dest
|
|
beq .Lw6
|
|
fail
|
|
.Lw6:
|
|
|
|
subx_l_imm32_0:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; subx.l #xx:32,Rd ; Subx with carry initially zero.
|
|
subx.l #0x50505, er0 ; Immediate 32-bit operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0xa5a0a0a0 er0 ; sub result:
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_imm32_1:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; subx.l #xx:32,Rd ; Subx with carry initially one.
|
|
set_carry_flag
|
|
subx.l #0x50504, er0 ; Immediate 32-bit operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0xa5a0a0a0 er0 ; sub result:
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_imm32_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l #xx:32,@eRd ; Subx to register indirect
|
|
mov #long_dest, er0
|
|
mov.l #0xa5a5a5a5, @er0
|
|
set_ccr_zero
|
|
subx.l #0x50505, @er0
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_dest er0 ; er0 still contains subress
|
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll1
|
|
fail
|
|
.Ll1:
|
|
|
|
subx_l_imm32_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l #xx:32,@eRd- ; Subx to register post-decrement
|
|
mov #long_dest, er0
|
|
mov.l #0xa5a5a5a5, @er0
|
|
set_ccr_zero
|
|
subx.l #0x50505, @er0-
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one
|
|
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll2
|
|
fail
|
|
.Ll2:
|
|
|
|
subx_l_reg32_0:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l Rs,Rd ; subx with carry initially zero
|
|
mov.l #0x50505, er0
|
|
set_ccr_zero
|
|
subx.l er0, er1 ; Register operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0x50505 er0 ; sub load
|
|
test_h_gr32 0xa5a0a0a0 er1 ; sub result:
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_reg32_1:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l Rs,Rd ; subx with carry initially one
|
|
mov.l #0x50504, er0
|
|
set_ccr_zero
|
|
set_carry_flag
|
|
subx.l er0, er1 ; Register operand
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 0x50504 er0 ; sub result:
|
|
test_h_gr32 0xa5a0a0a0 er1 ; sub result:
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_reg32_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l rs8,@eRd ; Subx to register indirect
|
|
mov #long_dest, er0
|
|
mov.l er1, @er0
|
|
mov.l #0x50505, er1
|
|
set_ccr_zero
|
|
subx.l er1, @er0
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_dest er0 ; er0 still contains subress
|
|
test_h_gr32 0x50505 er1 ; er1 has the test load
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll3
|
|
fail
|
|
.Ll3:
|
|
|
|
subx_l_reg32_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l rs8,@eRd- ; Subx to register post-decrement
|
|
mov #long_dest, er0
|
|
mov.l er1, @er0
|
|
mov.l #0x50505, er1
|
|
set_ccr_zero
|
|
subx.l er1, @er0-
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_dest-4 er0 ; er0 contains subress minus one
|
|
test_h_gr32 0x50505 er1 ; er1 contains the test load
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll4
|
|
fail
|
|
.Ll4:
|
|
|
|
subx_l_rsind_reg32:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l @eRs,rd8 ; Subx from reg indirect to reg
|
|
mov #long_src, er0
|
|
set_ccr_zero
|
|
subx.l @er0, er1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_src er0 ; er0 still contains subress
|
|
test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_rspostdec_reg32:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l @eRs-,rd8 ; Subx to register post-decrement
|
|
mov #long_src, er0
|
|
set_ccr_zero
|
|
subx.l @er0-, er1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_src-4 er0 ; er0 contains subress minus one
|
|
test_h_gr32 0xa5a0a0a0 er1 ; er1 contains the sum
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
subx_l_rsind_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l @eRs,rd8 ; Subx from reg indirect to reg
|
|
mov #long_src, er0
|
|
mov #long_dest, er1
|
|
mov.l er2, @er1
|
|
set_ccr_zero
|
|
subx.l @er0, @er1
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_src er0 ; er0 still contains src subress
|
|
test_h_gr32 long_dest er1 ; er1 still contains dst subress
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll5
|
|
fail
|
|
.Ll5:
|
|
|
|
subx_l_rspostdec_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
;; subx.l @eRs-,rd8 ; Subx to register post-decrement
|
|
mov #long_src, er0
|
|
mov #long_dest, er1
|
|
mov.l er2, @er1
|
|
set_ccr_zero
|
|
subx.l @er0-, @er1-
|
|
|
|
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
test_h_gr32 long_src-4 er0 ; er0 contains src subress minus one
|
|
test_h_gr32 long_dest-4 er1 ; er1 contains dst subress minus one
|
|
|
|
test_gr_a5a5 2 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
;; Now check the result of the sub to memory.
|
|
cmp.l #0xa5a0a0a0, @long_dest
|
|
beq .Ll6
|
|
fail
|
|
.Ll6:
|
|
.endif
|
|
pass
|
|
|
|
exit 0
|