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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
533 lines
11 KiB
ArmAsm
533 lines
11 KiB
ArmAsm
# Hitachi H8 testcase 'or.b'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# or.b #xx:8, rd ; c rd xxxxxxxx
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# or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
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# or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
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# or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
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# or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
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# or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
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# or.b rs, rd ; 1 4 rs rd
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# or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
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# or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
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# or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
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# or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
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# or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
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#
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# orc #xx:8, ccr
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# orc #xx:8, exr
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# Coming soon:
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# ...
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.data
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pre_byte: .byte 0
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byte_dest: .byte 0xa5
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post_byte: .byte 0
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start
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or_b_imm8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; or.b #xx:8,Rd
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or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5af r0 ; or result: a5 | aa
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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or_b_imm8_rdind:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b #xx:8,@eRd
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mov #byte_dest, er0
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or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x7d00
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;;; .word 0xc0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest, er0 ; er0 still contains address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L1
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fail
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.L1:
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or_b_imm8_rdpostinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b #xx:8,@eRd+
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mov #byte_dest, er0
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or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0xc055
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 post_byte, er0 ; er0 contains address plus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xf5, r0l
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beq .L2
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fail
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.L2:
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or_b_imm8_rdpostdec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b #xx:8,@eRd-
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mov #byte_dest, er0
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or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0xc0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 pre_byte, er0 ; er0 contains address minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L3
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fail
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.L3:
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or_b_imm8_rdpreinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b #xx:8,@+eRd
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mov #pre_byte, er0
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or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0xc055
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xf5, r0l
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beq .L4
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fail
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.L4:
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or_b_imm8_rdpredec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b #xx:8,@-eRd
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mov #post_byte, er0
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or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
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;;; .word 0x0177
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;;; .word 0x6c08
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;;; .word 0xc0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L5
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fail
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.L5:
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.endif
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or_b_reg8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; or.b Rs,Rd
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mov.b #0xaa, r0h
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or.b r0h, r0l ; Reg8 src, reg8 dest
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xaaaf r0 ; or result: a5 | aa
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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or_b_reg8_rdind:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b rs8,@eRd ; or reg8 to register indirect
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mov #byte_dest, er0
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mov #0xaa, r1l
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or.b r1l, @er0 ; reg8 src, reg indirect dest
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;;; .word 0x7d00
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;;; .word 0x1490
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 still contains address
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test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L6
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fail
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.L6:
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or_b_reg8_rdpostinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
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mov #byte_dest, er0
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mov #0x55, r1l
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or.b r1l, @er0+ ; reg8 src, reg post-incr dest
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;;; .word 0x0179
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;;; .word 0x8049
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 post_byte er0 ; er0 contains address plus one
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test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xf5, r0l
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beq .L7
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fail
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.L7:
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or_b_reg8_rdpostdec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
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mov #byte_dest, er0
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mov #0xaa, r1l
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or.b r1l, @er0- ; reg8 src, reg post-decr dest
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;;; .word 0x0179
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;;; .word 0xa049
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 pre_byte er0 ; er0 contains address minus one
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test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L8
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fail
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.L8:
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or_b_reg8_rdpreinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
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mov #pre_byte, er0
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mov #0x55, r1l
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or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
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;;; .word 0x0179
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;;; .word 0x9049
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xf5, r0l
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beq .L9
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fail
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.L9:
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or_b_reg8_rdpredec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
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mov #post_byte, er0
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mov #0xaa, r1l
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or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
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;;; .word 0x0179
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;;; .word 0xb049
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xaf, r0l
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beq .L10
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fail
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.L10:
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.endif
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orc_imm8_ccr:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; orc #xx:8,ccr
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test_neg_clear
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orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
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test_neg_set
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test_zero_clear
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orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
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test_zero_set
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test_ovf_clear
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orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
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test_ovf_set
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test_carry_clear
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orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
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test_carry_set
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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orc_imm8_exr:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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|
|
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ldc #0, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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|
|
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;; orc #xx:8,exr
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|
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orc #0x1, exr
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stc exr,r0l
|
|
test_h_gr8 1, r0l
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|
|
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orc #0x2, exr
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|
stc exr,r0l
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|
test_h_gr8 3, r0l
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|
|
|
orc #0x4, exr
|
|
stc exr,r0l
|
|
test_h_gr8 7, r0l
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|
|
|
orc #0x80, exr
|
|
stc exr,r0l
|
|
test_h_gr8 0x87, r0l
|
|
|
|
test_h_gr32 0xa5a5a587 er0
|
|
test_gr_a5a5 1 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
.endif ; not h8300 or h8300h
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|
|
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pass
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|
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exit 0
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