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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
138 lines
3.9 KiB
ArmAsm
138 lines
3.9 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp
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// Spec Reference: dsp32alu mix
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit
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// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
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imm32 r2, 0x44445555;
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imm32 r3, 0x66667777;
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imm32 r4, 0x88889999;
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imm32 r5, 0xaaaabbbb;
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imm32 r6, 0xccccdddd;
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imm32 r7, 0xeeeeffff;
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imm32 r0, 0x456789ab;
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imm32 r1, 0x6789abcd;
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// Use only single ALU (ALU0 only), with saturation (S)
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R2 = R1 + R0 (NS); /* 0xACF13578 */
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R3 = R2 + R0 (NS); /* 0xACF13578 */
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CHECKREG r2, 0xACF13578;
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CHECKREG r3, 0xF258BF23;
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R2 = R1 + R0 (S); /* 0x7FFFFFFF */
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R3 = R1 - R0 (NS); /* 0x22222222 */
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R4.L = R1.L + R0.L (NS); /* 0x88883578 */
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R5.L = R1.L + R0.H (NS); /* 0xAAAAF134 */
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R6.L = R1.H + R0.L (NS); /* 0xCCCCF134 */
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R7.L = R1.H + R0.H (NS); /* 0xEEEEACF0 */
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CHECKREG r2, 0x7FFFFFFF;
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CHECKREG r3, 0x22222222;
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CHECKREG r4, 0x88883578;
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CHECKREG r5, 0xAAAAF134;
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CHECKREG r6, 0xCCCCF134;
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CHECKREG r7, 0xEEEEACF0;
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R4.H = R1.L + R0.L (S); /* 0x80003578 */
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R5.H = R1.L + R0.H (S); /* 0xF134F134 */
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R6.H = R1.H + R0.L (S); /* 0xF134F134 */
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CHECKREG r4, 0x80003578;
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CHECKREG r5, 0xF134F134;
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CHECKREG r6, 0xF134F134;
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R4.H = R1.L + R0.L (S); /* 0x80003578 */
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R5.H = R1.L + R0.H (S); /* 0xF134F134 */
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R6.H = R1.H + R0.L (S); /* 0xF134F134 */
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CHECKREG r4, 0x80003578; /* 0x */
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CHECKREG r5, 0xF134F134; /* 0x */
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CHECKREG r6, 0xF134F134; /* 0x */
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R4.H = R1.L + R0.L (S); /* 0x80003578 */
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R5.H = R1.L + R0.H (S); /* 0xF134F134 */
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R6.H = R1.H + R0.L (S); /* 0xF134F134 */
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R7.H = R1.H + R0.H (S); /* 0x7FFFACF0 */
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CHECKREG r4, 0x80003578; /* 0x */
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CHECKREG r5, 0xF134F134; /* 0x */
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CHECKREG r6, 0xF134F134; /* 0x */
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CHECKREG r7, 0x7FFFACF0; /* 0x */
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// Dual
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R2 = R0 +|+ R1 (SCO); /* 0x80007FFF */
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R3 = R0 +|- R1 (S); /* 0x7FFFDDDE */
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R4 = R0 -|+ R1 (SCO); /* 0x8000DDDE)*/
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R5 = R0 -|- R1 (SCO); /* 0xDDDEDDDE */
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CHECKREG r2, 0x80007FFF;
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CHECKREG r3, 0x7FFFDDDE;
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CHECKREG r4, 0x8000DDDE;
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CHECKREG r5, 0xDDDEDDDE;
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R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO); /* 0x */
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CHECKREG r2, 0x7FFF8000;
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R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO); /* 0x */
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R6 = R0 + R1, R7 = R0 - R1 (S); /* 0x */
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CHECKREG r2, 0x7FFF8000;
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CHECKREG r3, 0xDDDEDDDE;
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CHECKREG r4, 0xACF0DDDE;
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CHECKREG r5, 0x3578DDDE;
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CHECKREG r6, 0x7FFFFFFF;
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CHECKREG r7, 0xDDDDDDDE;
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// Max min abs types
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R3 = MAX ( R0 , R1 ); /* 0x6789ABCD */
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R4 = MIN ( R0 , R1 ); /* 0x456789AB */
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R5 = ABS R0; /* 0x456789AB */
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CHECKREG r3, 0x6789ABCD;
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CHECKREG r4, 0x456789AB;
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CHECKREG r5, 0x456789AB;
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R3 = MAX ( R0 , R1 ) (V); /* 0x6789ABCD */
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R4 = MIN ( R0 , R1 ) (V); /* 0x456789AB */
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R5 = ABS R0 (V); /* 0x45677655 */
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CHECKREG r3, 0x6789ABCD;
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CHECKREG r4, 0x456789AB;
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CHECKREG r5, 0x45677655;
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// RND types
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R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L;
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R3.L = R0 + R1 (RND12); /* 0x */
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R4.H = R0 - R1 (RND12); /* 0x */
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R5.L = R0 + R1 (RND20); /* 0x */
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R6.H = R0 - R1 (RND20); /* 0x */
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R7.H = R1 (RND); /* 0x */
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CHECKREG r2, 0xBBBCBBBC;
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CHECKREG r3, 0x67897FFF;
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CHECKREG r4, 0x800089AB;
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CHECKREG r5, 0x45670ACF;
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CHECKREG r6, 0xFDDEFFFF;
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CHECKREG r7, 0x678ADDDE;
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R7 = - R0 (V); /* 0x */
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CHECKREG r7, 0xBA997655;
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// A0 & A1 types
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A0 = 0;
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A1 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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A0 = A1;
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A0.x = R0.L;
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A1.x = R0.L;
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R2.L = A0.x; /* 0x */
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R3.L = A1.x; /* 0x */
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R4 = ( A0 += A1 ); /* 0x */
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R5.L = ( A0 += A1 ); /* 0x */
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R5.H = ( A0 += A1 ); /* 0x */
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CHECKREG r2, 0xBBBCffAB; /* 0x */
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CHECKREG r3, 0x6789ffAB; /* 0x */
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CHECKREG r4, 0x80000000; /* 0x */
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CHECKREG r5, 0x80008000; /* 0x */
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A0 += A1;
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A0 -= A1;
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R6 = A1.L + A1.H, R7 = A0.L + A0.H; /* 0x */
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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pass
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