mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-03 04:12:10 +08:00
7ba29e2a41
* bfd/Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}.
* bfd/Makefile.in: Same.
* bfd/archures.c: Add bfd_arch_microblaze.
* bfd/bfd-in2.h: Regenerate.
* bfd/config.bfd: Add microblaze target.
* bfd/configure: Add bfd_elf32_microblaze_vec target.
* bfd/configure.in: Same.
* bfd/cpu-microblaze.c: New.
* bfd/elf32-microblaze.c: New.
* bfd/libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc().
* bfd/libbfd.h: Regenerate.
* bfd/reloc.c: Add MICROBLAZE relocations.
* bfd/section.c: Add struct relax_table and relax_count to section.
* bfd/targets.c: Add bfd_elf32_microblaze_vec.
* binutils/MAINTAINERS: Add self as maintainer.
* binutils/readelf.c: Include elf/microblaze.h, add EM_MICROBLAZE &
EM_MICROBLAZE_OLD to guess_is_rela(), dump_relocations(),
get_machine_name().
* config.sub: Add microblaze target.
* configure: Same.
* configure.ac: Same.
* gas/Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to
TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add
DEP_microblaze_elf target.
* gas/Makefile.in: Same.
* gas/config/tc-microblaze.c: Add MicroBlaze assembler.
* gas/config/tc-microblaze.h: Add header for tc-microblaze.c.
* gas/configure: Add microblaze target.
* gas/configure.in: Same.
* gas/configure.tgt: Same.
* gas/doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS.
* gas/doc/Makefile.in: Same.
* gas/doc/all.texi: Set MICROBLAZE.
* gas/doc/as.texinfo: Add MicroBlaze doc links.
* gas/doc/c-microblaze.texi: New MicroBlaze docs.
* include/dis-asm.h: Decl print_insn_microblaze().
* include/elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
* include/elf/microblaze.h: New reloc definitions.
* ld/Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to
ALL_EMULATIONS, targets.
* ld/Makefile.in: Same.
* ld/configure.tgt: Add microblaze*-linux*, microblaze* targets.
* ld/emulparams/elf32mb_linux.sh: New.
* ld/emulparams/elf32microblaze.sh. New.
* ld/scripttempl/elfmicroblaze.sc: New.
* opcodes/Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to
CFILES, microblaze-dis.lo to ALL_MACHINES, targets.
* opcodes/Makefile.in: Same.
* opcodes/configure: Add bfd_microblaze_arch target.
* opcodes/configure.in: Same.
* opcodes/disassemble.c: Define ARCH_microblaze, return
print_insn_microblaze().
* opcodes/microblaze-dis.c: New MicroBlaze disassembler.
* opcodes/microblaze-opc.h: New MicroBlaze opcode definitions.
* opcodes/microblaze-opcm.h: New MicroBlaze opcode types.
528 lines
14 KiB
C
528 lines
14 KiB
C
/* Disassemble Xilinx microblaze instructions.
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Copyright 2009 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#include "microblaze-opc.h"
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#include "dis-asm.h"
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#include <strings.h>
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#define get_field_rd(instr) get_field (instr, RD_MASK, RD_LOW)
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#define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW)
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#define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW)
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#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
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#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
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static char *
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get_field (long instr, long mask, unsigned short low)
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{
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char tmpstr[25];
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sprintf (tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
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return (strdup (tmpstr));
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}
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static char *
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get_field_imm (long instr)
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{
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char tmpstr[25];
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sprintf (tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
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return (strdup (tmpstr));
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}
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static char *
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get_field_imm5 (long instr)
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{
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char tmpstr[25];
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sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
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return (strdup (tmpstr));
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}
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static char *
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get_field_rfsl (long instr)
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{
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char tmpstr[25];
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sprintf (tmpstr, "%s%d", fsl_register_prefix,
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(short)((instr & RFSL_MASK) >> IMM_LOW));
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return (strdup (tmpstr));
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}
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static char *
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get_field_imm15 (long instr)
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{
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char tmpstr[25];
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sprintf (tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
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return (strdup (tmpstr));
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}
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static char *
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get_field_special (long instr, struct op_code_struct * op)
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{
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char tmpstr[25];
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char spr[6];
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switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
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{
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case REG_MSR_MASK :
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strcpy (spr, "msr");
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break;
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case REG_PC_MASK :
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strcpy (spr, "pc");
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break;
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case REG_EAR_MASK :
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strcpy (spr, "ear");
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break;
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case REG_ESR_MASK :
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strcpy (spr, "esr");
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break;
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case REG_FSR_MASK :
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strcpy (spr, "fsr");
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break;
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case REG_BTR_MASK :
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strcpy (spr, "btr");
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break;
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case REG_EDR_MASK :
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strcpy (spr, "edr");
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break;
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case REG_PID_MASK :
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strcpy (spr, "pid");
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break;
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case REG_ZPR_MASK :
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strcpy (spr, "zpr");
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break;
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case REG_TLBX_MASK :
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strcpy (spr, "tlbx");
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break;
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case REG_TLBLO_MASK :
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strcpy (spr, "tlblo");
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break;
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case REG_TLBHI_MASK :
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strcpy (spr, "tlbhi");
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break;
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case REG_TLBSX_MASK :
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strcpy (spr, "tlbsx");
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break;
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default :
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if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
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== REG_PVR_MASK)
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{
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sprintf (tmpstr, "%spvr%d", register_prefix,
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(unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
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^ op->immval_mask) ^ REG_PVR_MASK);
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return (strdup (tmpstr));
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}
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else
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strcpy (spr, "pc");
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break;
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}
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sprintf (tmpstr, "%s%s", register_prefix, spr);
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return (strdup (tmpstr));
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}
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static unsigned long
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read_insn_microblaze (bfd_vma memaddr,
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struct disassemble_info *info,
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struct op_code_struct **opr)
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{
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unsigned char ibytes[4];
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int status;
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struct op_code_struct * op;
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unsigned long inst;
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status = info->read_memory_func (memaddr, ibytes, 4, info);
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return 0;
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}
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if (info->endian == BFD_ENDIAN_BIG)
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inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3];
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else if (info->endian == BFD_ENDIAN_LITTLE)
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inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0];
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else
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abort ();
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/* Just a linear search of the table. */
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for (op = opcodes; op->name != 0; op ++)
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if (op->bit_sequence == (inst & op->opcode_mask))
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break;
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*opr = op;
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return inst;
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}
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int
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print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
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{
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fprintf_ftype fprintf = info->fprintf_func;
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void * stream = info->stream;
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unsigned long inst, prev_inst;
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struct op_code_struct * op, *pop;
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int immval = 0;
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bfd_boolean immfound = FALSE;
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static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */
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static int prev_insn_vma = -1; /* Init the prev insn vma. */
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int curr_insn_vma = info->buffer_vma;
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info->bytes_per_chunk = 4;
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inst = read_insn_microblaze (memaddr, info, &op);
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if (inst == 0)
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return -1;
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if (prev_insn_vma == curr_insn_vma)
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{
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if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
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{
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prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
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if (prev_inst == 0)
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return -1;
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if (pop->instr == imm)
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{
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immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
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immfound = TRUE;
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}
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else
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{
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immval = 0;
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immfound = FALSE;
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}
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}
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}
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/* Make curr insn as prev insn. */
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prev_insn_addr = memaddr;
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prev_insn_vma = curr_insn_vma;
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if (op->name == NULL)
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fprintf (stream, ".short 0x%04x", inst);
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else
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{
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fprintf (stream, "%s", op->name);
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switch (op->inst_type)
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{
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case INST_TYPE_RD_R1_R2:
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fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
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get_field_r1(inst), get_field_r2 (inst));
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break;
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case INST_TYPE_RD_R1_IMM:
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fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
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get_field_r1(inst), get_field_imm (inst));
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if (info->print_address_func && get_int_field_r1 (inst) == 0
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&& info->symbol_at_address_func)
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{
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if (immfound)
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immval |= (get_int_field_imm (inst) & 0x0000ffff);
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else
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{
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immval = get_int_field_imm (inst);
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if (immval & 0x8000)
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immval |= 0xFFFF0000;
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}
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if (immval > 0 && info->symbol_at_address_func (immval, info))
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{
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fprintf (stream, "\t// ");
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info->print_address_func (immval, info);
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}
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}
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break;
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case INST_TYPE_RD_R1_IMM5:
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fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
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get_field_r1(inst), get_field_imm5 (inst));
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break;
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case INST_TYPE_RD_RFSL:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst));
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break;
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case INST_TYPE_R1_RFSL:
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fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst));
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break;
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case INST_TYPE_RD_SPECIAL:
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fprintf (stream, "\t%s, %s", get_field_rd (inst),
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get_field_special (inst, op));
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break;
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case INST_TYPE_SPECIAL_R1:
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fprintf (stream, "\t%s, %s", get_field_special (inst, op),
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get_field_r1(inst));
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break;
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case INST_TYPE_RD_R1:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst));
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break;
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case INST_TYPE_R1_R2:
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fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
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break;
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case INST_TYPE_R1_IMM:
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fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst));
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/* The non-pc relative instructions are returns, which shouldn't
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have a label printed. */
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if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
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&& info->symbol_at_address_func)
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{
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if (immfound)
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immval |= (get_int_field_imm (inst) & 0x0000ffff);
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else
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{
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immval = get_int_field_imm (inst);
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if (immval & 0x8000)
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immval |= 0xFFFF0000;
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}
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immval += memaddr;
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if (immval > 0 && info->symbol_at_address_func (immval, info))
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{
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fprintf (stream, "\t// ");
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info->print_address_func (immval, info);
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}
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else
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{
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fprintf (stream, "\t\t// ");
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fprintf (stream, "%x", immval);
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}
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}
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break;
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case INST_TYPE_RD_IMM:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst));
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if (info->print_address_func && info->symbol_at_address_func)
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{
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if (immfound)
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immval |= (get_int_field_imm (inst) & 0x0000ffff);
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else
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{
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immval = get_int_field_imm (inst);
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if (immval & 0x8000)
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immval |= 0xFFFF0000;
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}
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if (op->inst_offset_type == INST_PC_OFFSET)
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immval += (int) memaddr;
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if (info->symbol_at_address_func (immval, info))
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{
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fprintf (stream, "\t// ");
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info->print_address_func (immval, info);
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}
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}
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break;
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case INST_TYPE_IMM:
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fprintf (stream, "\t%s", get_field_imm (inst));
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if (info->print_address_func && info->symbol_at_address_func
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&& op->instr != imm)
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{
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if (immfound)
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immval |= (get_int_field_imm (inst) & 0x0000ffff);
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else
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{
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immval = get_int_field_imm (inst);
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if (immval & 0x8000)
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immval |= 0xFFFF0000;
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}
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if (op->inst_offset_type == INST_PC_OFFSET)
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immval += (int) memaddr;
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if (immval > 0 && info->symbol_at_address_func (immval, info))
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{
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fprintf (stream, "\t// ");
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info->print_address_func (immval, info);
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}
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else if (op->inst_offset_type == INST_PC_OFFSET)
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{
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fprintf (stream, "\t\t// ");
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fprintf (stream, "%x", immval);
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}
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}
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break;
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case INST_TYPE_RD_R2:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
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break;
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case INST_TYPE_R2:
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fprintf (stream, "\t%s", get_field_r2 (inst));
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break;
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case INST_TYPE_R1:
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fprintf (stream, "\t%s", get_field_r1 (inst));
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break;
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case INST_TYPE_RD_R1_SPECIAL:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
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break;
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case INST_TYPE_RD_IMM15:
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fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
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break;
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/* For tuqula instruction */
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case INST_TYPE_RD:
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fprintf (stream, "\t%s", get_field_rd (inst));
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break;
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case INST_TYPE_RFSL:
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fprintf (stream, "\t%s", get_field_rfsl (inst));
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break;
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default:
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/* If the disassembler lags the instruction set. */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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break;
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}
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}
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/* Say how many bytes we consumed. */
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return 4;
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}
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#if 0
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static enum microblaze_instr
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get_insn_microblaze (long inst,
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bfd_boolean *isunsignedimm,
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enum microblaze_instr_type *insn_type,
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short *delay_slots)
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{
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struct op_code_struct * op;
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*isunsignedimm = FALSE;
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/* Just a linear search of the table. */
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for (op = opcodes; op->name != 0; op ++)
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if (op->bit_sequence == (inst & op->opcode_mask))
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break;
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if (op->name == 0)
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return invalid_inst;
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else
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{
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*isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
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*insn_type = op->instr_type;
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*delay_slots = op->delay_slots;
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return op->instr;
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}
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}
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short
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get_delay_slots_microblaze (long inst)
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{
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bfd_boolean isunsignedimm;
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enum microblaze_instr_type insn_type;
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enum microblaze_instr op;
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short delay_slots;
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op = get_insn_microblaze (inst, &isunsignedimm, &insn_type, &delay_slots);
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if (op == invalid_inst)
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return 0;
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else
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return delay_slots;
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}
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enum microblaze_instr
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microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
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{
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enum microblaze_instr op;
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bfd_boolean t1;
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enum microblaze_instr_type t2;
|
|
short t3;
|
|
|
|
op = get_insn_microblaze (insn, &t1, &t2, &t3);
|
|
*rd = (insn & RD_MASK) >> RD_LOW;
|
|
*ra = (insn & RA_MASK) >> RA_LOW;
|
|
*rb = (insn & RB_MASK) >> RB_LOW;
|
|
t3 = (insn & IMM_MASK) >> IMM_LOW;
|
|
*imm = (int) t3;
|
|
return (op);
|
|
}
|
|
|
|
unsigned long
|
|
microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
|
|
long pcval, long r1val, long r2val,
|
|
bfd_boolean *targetvalid,
|
|
bfd_boolean *unconditionalbranch)
|
|
{
|
|
struct op_code_struct * op;
|
|
long targetaddr = 0;
|
|
|
|
*unconditionalbranch = FALSE;
|
|
/* Just a linear search of the table. */
|
|
for (op = opcodes; op->name != 0; op ++)
|
|
if (op->bit_sequence == (inst & op->opcode_mask))
|
|
break;
|
|
|
|
if (op->name == 0)
|
|
{
|
|
*targetvalid = FALSE;
|
|
}
|
|
else if (op->instr_type == branch_inst)
|
|
{
|
|
switch (op->inst_type)
|
|
{
|
|
case INST_TYPE_R2:
|
|
*unconditionalbranch = TRUE;
|
|
/* Fall through. */
|
|
case INST_TYPE_RD_R2:
|
|
case INST_TYPE_R1_R2:
|
|
targetaddr = r2val;
|
|
*targetvalid = TRUE;
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
targetaddr += pcval;
|
|
break;
|
|
case INST_TYPE_IMM:
|
|
*unconditionalbranch = TRUE;
|
|
/* Fall through. */
|
|
case INST_TYPE_RD_IMM:
|
|
case INST_TYPE_R1_IMM:
|
|
if (immfound)
|
|
{
|
|
targetaddr = (immval << 16) & 0xffff0000;
|
|
targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
|
|
}
|
|
else
|
|
{
|
|
targetaddr = get_int_field_imm (inst);
|
|
if (targetaddr & 0x8000)
|
|
targetaddr |= 0xFFFF0000;
|
|
}
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
targetaddr += pcval;
|
|
*targetvalid = TRUE;
|
|
break;
|
|
default:
|
|
*targetvalid = FALSE;
|
|
break;
|
|
}
|
|
}
|
|
else if (op->instr_type == return_inst)
|
|
{
|
|
if (immfound)
|
|
{
|
|
targetaddr = (immval << 16) & 0xffff0000;
|
|
targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
|
|
}
|
|
else
|
|
{
|
|
targetaddr = get_int_field_imm (inst);
|
|
if (targetaddr & 0x8000)
|
|
targetaddr |= 0xFFFF0000;
|
|
}
|
|
targetaddr += r1val;
|
|
*targetvalid = TRUE;
|
|
}
|
|
else
|
|
*targetvalid = FALSE;
|
|
return targetaddr;
|
|
}
|
|
#endif
|