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0ef0eba580
(lookup_hash): Call hash rather than computing the hash
code here.
(do_format_1_2): Handle format 1 and format 2 instructions.
Get operands correctly and call the target function.
(do_format_6): Get operands correctly and call the target
function.
(do_formats_9_10): Rough cut so shift ops will work.
(sim_resume): Tweak to deal with format 1 and format 2
handling in a single funtion. Don't update the PC
for format 3 insns. Fix typos.
* simops.c: Slightly reorganize. Add condition code handling
to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
and "not" instructions.
* v850_sim.h (reg_t): Registers are 32bits.
(_state): The V850 has 32 general registers. Add a 32bit
psw and pc register too. Add accessor macros
Fixing lots of stuff. Starting to add condition code support. Basically
check pointing the work to date.
37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (hash): Update to be more accurate.
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(lookup_hash): Call hash rather than computing the hash
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code here.
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(do_format_1_2): Handle format 1 and format 2 instructions.
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Get operands correctly and call the target function.
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(do_format_6): Get operands correctly and call the target
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function.
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(do_formats_9_10): Rough cut so shift ops will work.
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(sim_resume): Tweak to deal with format 1 and format 2
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handling in a single funtion. Don't update the PC
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for format 3 insns. Fix typos.
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* simops.c: Slightly reorganize. Add condition code handling
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to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
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and "not" instructions.
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* v850_sim.h (reg_t): Registers are 32bits.
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(_state): The V850 has 32 general registers. Add a 32bit
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psw and pc register too. Add accessor macros
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* Makefile.in, interp.c, v850_sim.h: Bring over endianness
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changes from the d10v simulator.
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* simops.c: Add shift support.
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* simops.c: Add multiply & divide support. Abort for system
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instructions.
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* simops.c: Add logicals, mov, movhi, movea, add, addi, sub
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and subr. No condition codes yet.
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Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
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* ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
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gencode.c, interp.c, simops.c: Created.
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