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8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
263 lines
6.9 KiB
C
263 lines
6.9 KiB
C
/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
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For "new style" UARTs on BF50x/BF54x parts.
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Copyright (C) 2010-2013 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_uart2.h"
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/* XXX: Should we bother emulating the TX/RX FIFOs ? */
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/* Internal state needs to be the same as bfin_uart. */
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struct bfin_uart
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{
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/* This top portion matches common dv_bfin struct. */
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bu32 base;
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struct hw *dma_master;
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bool acked;
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struct hw_event *handler;
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char saved_byte;
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int saved_count;
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/* Accessed indirectly by ier_{set,clear}. */
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bu16 ier;
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(dll);
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bu16 BFIN_MMR_16(dlh);
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bu16 BFIN_MMR_16(gctl);
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bu16 BFIN_MMR_16(lcr);
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bu16 BFIN_MMR_16(mcr);
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bu16 BFIN_MMR_16(lsr);
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bu16 BFIN_MMR_16(msr);
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bu16 BFIN_MMR_16(scr);
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bu16 BFIN_MMR_16(ier_set);
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bu16 BFIN_MMR_16(ier_clear);
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bu16 BFIN_MMR_16(thr);
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bu16 BFIN_MMR_16(rbr);
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};
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#define mmr_base() offsetof(struct bfin_uart, dll)
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#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"UART_DLL", "UART_DLH", "UART_GCTL", "UART_LCR", "UART_MCR", "UART_LSR",
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"UART_MSR", "UART_SCR", "UART_IER_SET", "UART_IER_CLEAR", "UART_THR",
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"UART_RBR",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_uart_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_uart *uart = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *valuep;
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value = dv_load_2 (source);
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mmr_off = addr - uart->base;
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valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
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switch (mmr_off)
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{
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case mmr_offset(thr):
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uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
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if (uart->ier & ETBEI)
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hw_port_event (me, DV_PORT_TX, 1);
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break;
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case mmr_offset(ier_set):
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uart->ier |= value;
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break;
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case mmr_offset(ier_clear):
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dv_w1c_2 (&uart->ier, value, -1);
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break;
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case mmr_offset(lsr):
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dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE);
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break;
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case mmr_offset(rbr):
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/* XXX: Writes are ignored ? */
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break;
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case mmr_offset(msr):
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dv_w1c_2 (valuep, value, SCTS);
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break;
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case mmr_offset(dll):
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case mmr_offset(dlh):
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case mmr_offset(gctl):
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case mmr_offset(lcr):
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case mmr_offset(mcr):
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case mmr_offset(scr):
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*valuep = value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_uart_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_uart *uart = hw_data (me);
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bu32 mmr_off;
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bu16 *valuep;
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mmr_off = addr - uart->base;
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valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
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switch (mmr_off)
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{
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case mmr_offset(rbr):
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uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, uart->mcr, NULL);
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dv_store_2 (dest, uart->rbr);
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break;
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case mmr_offset(ier_set):
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case mmr_offset(ier_clear):
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dv_store_2 (dest, uart->ier);
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bfin_uart_reschedule (me);
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break;
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case mmr_offset(lsr):
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uart->lsr &= ~(DR | THRE | TEMT);
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uart->lsr |= bfin_uart_get_status (me);
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case mmr_offset(thr):
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case mmr_offset(msr):
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case mmr_offset(dll):
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case mmr_offset(dlh):
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case mmr_offset(gctl):
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case mmr_offset(lcr):
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case mmr_offset(mcr):
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case mmr_offset(scr):
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dv_store_2 (dest, *valuep);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space,
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unsigned_word addr, unsigned nr_bytes)
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{
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HW_TRACE_DMA_READ ();
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return bfin_uart_read_buffer (me, dest, nr_bytes);
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}
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static unsigned
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bfin_uart_dma_write_buffer (struct hw *me, const void *source,
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int space, unsigned_word addr,
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unsigned nr_bytes,
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int violate_read_only_section)
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{
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struct bfin_uart *uart = hw_data (me);
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unsigned ret;
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HW_TRACE_DMA_WRITE ();
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ret = bfin_uart_write_buffer (me, source, nr_bytes);
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if (ret == nr_bytes && (uart->ier & ETBEI))
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hw_port_event (me, DV_PORT_TX, 1);
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return ret;
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}
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static const struct hw_port_descriptor bfin_uart_ports[] =
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{
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{ "tx", DV_PORT_TX, 0, output_port, },
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{ "rx", DV_PORT_RX, 0, output_port, },
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{ "stat", DV_PORT_STAT, 0, output_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_UART2_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART2_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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uart->base = attach_address;
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}
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static void
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bfin_uart_finish (struct hw *me)
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{
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struct bfin_uart *uart;
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uart = HW_ZALLOC (me, struct bfin_uart);
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set_hw_data (me, uart);
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set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
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set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
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set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
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set_hw_ports (me, bfin_uart_ports);
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attach_bfin_uart_regs (me, uart);
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/* Initialize the UART. */
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uart->dll = 0x0001;
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uart->lsr = 0x0060;
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}
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const struct hw_descriptor dv_bfin_uart2_descriptor[] =
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{
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{"bfin_uart2", bfin_uart_finish,},
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{NULL, NULL},
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};
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