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Our interpretation of the layout of floating-point general registers (FGRs) in o32 MIPS/Linux core files is different from how the kernel makes them, affecting the CP0 Status.FR=0 aka FP32 mode (we don't currently support the CP0 Status.FR=1 aka FP64 mode with the o32 ABI). In the FP32 mode pairs of consecutive even/odd-numbered 32-bit registers are placed together as 64-bit values in even-indexed 64-bit slots corresponding to the even index, leaving the odd-indexed 64-bit slots unused. These 64-bit values are stored according to the endianness in effect, which is how the MIPS II SDC1 instruction would store them. It has always been like that with the Linux kernel for MIPS II and higher ISA processors, which are the vast majority ever supported, as it is indeed SDC1 that the kernel uses to store FGRs in a floating-point context. With MIPS I processors, which lack the SDC1 instruction, a layout that we expect used to be used long ago, but it was corrected for consistency with newer processors back in 2002, with `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU ptrace() handling fixes."), and then broken and fixed over and over again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct MIPS I FP context layout"). Consequently the values we see in FP32 core files or produce with the `gcore' command are different from those obtained from the same FP context of a live process, e.g. with a big-endian configuration these live values: (gdb) info registers float f0: 0x4b5c6d7e flt: 14445950 dbl: 1.7446153562345001e-274 f1: 0x0718293a flt: 1.14473244e-34 f2: 0xc3d4e5f6 flt: -425.79657 dbl: -1.046160437414959e-233 f3: 0x8f90a1b2 flt: -1.42617791e-29 f4: 0x4c5d6e7f flt: 58046972 dbl: 1.1908587841220294e-269 f5: 0x08192a3b flt: 4.60914044e-34 f6: 0xc4d5e6f7 flt: -1711.21765 dbl: -6.2784661835068965e-306 f7: 0x8091a2b3 flt: -1.33745124e-38 f8: 0x45566778 flt: 3430.4668 dbl: 1.6530355595710607e-303 f9: 0x01122334 flt: 2.68412219e-38 f10: 0xcddeeff0 flt: -467533312 dbl: -2.1174864564135575e-262 f11: 0x899aabbc flt: -3.72356497e-33 f12: 0x46576879 flt: 13786.1182 dbl: 1.143296486773654e-298 f13: 0x02132435 flt: 1.08102453e-37 f14: 0xcedfe0f1 flt: -1.87803046e+09 dbl: -1.4399511533369862e-257 f15: 0x8a9bacbd flt: -1.4990934e-32 f16: 0x4758697a flt: 55401.4766 dbl: 7.8856820439568725e-294 f17: 0x03142536 flt: 4.3536007e-37 f18: 0xcfd0e1f2 flt: -7.00893696e+09 dbl: -9.7791926757340559e-253 f19: 0x8b9cadbe flt: -6.03504325e-32 f20: 0x48596a7b flt: 222633.922 dbl: 5.4255001483306113e-289 f21: 0x04152637 flt: 1.75324132e-36 f22: 0xc0d1e2f3 flt: -6.55895376 dbl: -6.6332401002310683e-248 f23: 0x8c9daebf flt: -2.42948516e-31 f24: 0x495a6b7c flt: 894647.75 dbl: 3.7244369058749787e-284 f25: 0x05162738 flt: 7.06016945e-36 f26: 0xc1d2e3f4 flt: -26.3613052 dbl: -4.4941535759306202e-243 f27: 0x8d9eafb0 flt: -9.77979703e-31 f28: 0x4a5b6c7d flt: 3595039.25 dbl: 2.5514593711161396e-279 f29: 0x06172839 flt: 2.84294945e-35 f30: 0xc2d3e4f5 flt: -105.947182 dbl: -3.035646690850097e-238 f31: 0x8e9fa0b1 flt: -3.93512664e-30 fcsr: 0x0 fir: 0xf30000 (gdb) show up in a core file as these: (gdb) info registers float f0: 0x0718293a flt: 1.14473244e-34 dbl: nan f1: 0x7ff80000 flt: nan f2: 0x8f90a1b2 flt: -1.42617791e-29 dbl: nan f3: 0x7ff80000 flt: nan f4: 0x08192a3b flt: 4.60914044e-34 dbl: nan f5: 0x7ff80000 flt: nan f6: 0x8091a2b3 flt: -1.33745124e-38 dbl: nan f7: 0x7ff80000 flt: nan f8: 0x01122334 flt: 2.68412219e-38 dbl: nan f9: 0x7ff80000 flt: nan f10: 0x899aabbc flt: -3.72356497e-33 dbl: nan f11: 0x7ff80000 flt: nan f12: 0x02132435 flt: 1.08102453e-37 dbl: nan f13: 0x7ff80000 flt: nan f14: 0x8a9bacbd flt: -1.4990934e-32 dbl: nan f15: 0x7ff80000 flt: nan f16: 0x03142536 flt: 4.3536007e-37 dbl: nan f17: 0x7ff80000 flt: nan f18: 0x8b9cadbe flt: -6.03504325e-32 dbl: nan f19: 0x7ff80000 flt: nan f20: 0x04152637 flt: 1.75324132e-36 dbl: nan f21: 0x7ff80000 flt: nan f22: 0x8c9daebf flt: -2.42948516e-31 dbl: nan f23: 0x7ff80000 flt: nan f24: 0x05162738 flt: 7.06016945e-36 dbl: nan f25: 0x7ff80000 flt: nan f26: 0x8d9eafb0 flt: -9.77979703e-31 dbl: nan f27: 0x7ff80000 flt: nan f28: 0x06172839 flt: 2.84294945e-35 dbl: nan f29: 0x7ff80000 flt: nan f30: 0x8e9fa0b1 flt: -3.93512664e-30 dbl: nan f31: 0x7ff80000 flt: nan (gdb) Notice how values from odd-numbered registers are shown in corresponding even-numbered registers and how dummy 0x7ff80000 NaN values, which the kernel places in unused slots, are reported in odd-numbered registers. Correct our intepretation then, to match the kernel's. As it happens the o32 FGR core file representation matches that used by the `ptrace' PTRACE_GETFPREGS request, which means our 64-bit handlers can be readily used, as they already correctly handle the differences between o32 FP32 mode vs n32/n64 representations. Adjust comments accordingly throughout, in particular remove a reference to the r3000/tx39 MIPS I processor peculiarity, long irrelevant. Add a test case to verify correctness. Avoid GCC bugs and limitations in the test case where possible; the test case still fails to build with GCC 8 and the o32 FP64 mode (i.e. with `-mips32r2 -mfp64' options) giving: mips-fpregset-core.c: In function 'main': mips-fpregset-core.c:66:3: error: inconsistent operand constraints in an 'asm' asm ( ^~~ (GCC PR target/85909), but that is not a concern for us as yet, because as noted above we do not currently support the o32 FP64 mode anyway. gdb/ * mips-linux-tdep.h (mips_supply_fpregset, mips_fill_fpregset): Remove prototypes. * mips-linux-nat.c (supply_fpregset): Always call `mips64_supply_fpregset' rather than `mips_supply_fpregset'. (fill_fpregset): Always call `mips64_fill_fpregset' rather than `mips_fill_fpregset'. * mips-linux-tdep.c (mips_supply_fpregset) (mips_supply_fpregset_wrapper, mips_fill_fpregset) (mips_fill_fpregset_wrapper): Remove functions. (mips64_supply_fpregset, mips64_fill_fpregset): Update comments. (mips_linux_fpregset): Remove variable. (mips_linux_iterate_over_regset_sections): Use `mips64_linux_fpregset' in place of `mips_linux_fpregset'. (mips_linux_o32_sigframe_init): Remove comment. gdb/testsuite/ * gdb.arch/mips-fpregset-core.exp: New test. * gdb.arch/mips-fpregset-core.c: New test source.
112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/* Target-dependent code for GNU/Linux on MIPS processors.
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Copyright (C) 2006-2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* Copied from <asm/elf.h>. */
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#define ELF_NGREG 45
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#define ELF_NFPREG 33
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typedef unsigned char mips_elf_greg_t[4];
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typedef mips_elf_greg_t mips_elf_gregset_t[ELF_NGREG];
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typedef unsigned char mips_elf_fpreg_t[8];
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typedef mips_elf_fpreg_t mips_elf_fpregset_t[ELF_NFPREG];
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/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
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#define FPR_BASE 32
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#define PC 64
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#define CAUSE 65
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#define BADVADDR 66
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#define MMHI 67
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#define MMLO 68
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#define FPC_CSR 69
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#define FPC_EIR 70
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#define DSP_BASE 71
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#define DSP_CONTROL 77
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#define EF_REG0 6
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#define EF_REG31 37
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#define EF_LO 38
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#define EF_HI 39
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#define EF_CP0_EPC 40
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#define EF_CP0_BADVADDR 41
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#define EF_CP0_STATUS 42
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#define EF_CP0_CAUSE 43
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#define EF_SIZE 180
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void mips_supply_gregset (struct regcache *, const mips_elf_gregset_t *);
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void mips_fill_gregset (const struct regcache *, mips_elf_gregset_t *, int);
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/* 64-bit support. */
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/* Copied from <asm/elf.h>. */
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#define MIPS64_ELF_NGREG 45
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#define MIPS64_ELF_NFPREG 33
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typedef unsigned char mips64_elf_greg_t[8];
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typedef mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG];
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typedef unsigned char mips64_elf_fpreg_t[8];
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typedef mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG];
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/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
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#define MIPS64_FPR_BASE 32
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#define MIPS64_PC 64
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#define MIPS64_CAUSE 65
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#define MIPS64_BADVADDR 66
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#define MIPS64_MMHI 67
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#define MIPS64_MMLO 68
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#define MIPS64_FPC_CSR 69
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#define MIPS64_FPC_EIR 70
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#define MIPS64_EF_REG0 0
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#define MIPS64_EF_REG31 31
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#define MIPS64_EF_LO 32
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#define MIPS64_EF_HI 33
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#define MIPS64_EF_CP0_EPC 34
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#define MIPS64_EF_CP0_BADVADDR 35
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#define MIPS64_EF_CP0_STATUS 36
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#define MIPS64_EF_CP0_CAUSE 37
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#define MIPS64_EF_SIZE 304
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void mips64_supply_gregset (struct regcache *, const mips64_elf_gregset_t *);
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void mips64_fill_gregset (const struct regcache *,
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mips64_elf_gregset_t *, int);
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void mips64_supply_fpregset (struct regcache *,
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const mips64_elf_fpregset_t *);
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void mips64_fill_fpregset (const struct regcache *,
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mips64_elf_fpregset_t *, int);
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enum {
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/* The Linux kernel stores an error code from any interrupted
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syscall in a "register" (in $0's save slot). */
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MIPS_RESTART_REGNUM = 79
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};
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/* Return 1 if MIPS_RESTART_REGNUM is usable. */
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int mips_linux_restart_reg_p (struct gdbarch *gdbarch);
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/* Target descriptions. */
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extern struct target_desc *tdesc_mips_linux;
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extern struct target_desc *tdesc_mips64_linux;
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extern struct target_desc *tdesc_mips_dsp_linux;
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extern struct target_desc *tdesc_mips64_dsp_linux;
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