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253 lines
7.5 KiB
C
253 lines
7.5 KiB
C
/* Simulator pseudo baseclass.
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Copyright (C) 1997-1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* Simulator state pseudo baseclass.
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Each simulator is required to have the file ``sim-main.h''. That
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file includes ``sim-basics.h'', defines the base type ``sim_cia''
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(the data type that contains complete current instruction address
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information), include ``sim-base.h'':
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#include "sim-basics.h"
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typedef address_word sim_cia;
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/-* If `sim_cia' is not an integral value (e.g. a struct), define
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CIA_ADDR to return the integral value. *-/
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/-* #define CIA_ADDR(cia) (...) *-/
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#include "sim-base.h"
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finally, two data types `struct _sim_cpu' and `struct sim_state'
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are defined:
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struct _sim_cpu {
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... simulator specific members ...
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sim_cpu_base base;
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};
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struct sim_state {
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sim_cpu cpu[MAX_NR_PROCESSORS];
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#if (WITH_SMP)
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#define STATE_CPU(sd,n) (&(sd)->cpu[n])
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#else
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#define STATE_CPU(sd,n) (&(sd)->cpu[0])
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#endif
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... simulator specific members ...
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sim_state_base base;
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};
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Note that `base' appears last. This makes `base.magic' appear last
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in the entire struct and helps catch miscompilation errors. */
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#ifndef SIM_BASE_H
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#define SIM_BASE_H
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/* Pre-declare certain types. */
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/* typedef <target-dependant> sim_cia; */
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#ifndef NULL_CIA
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#define NULL_CIA ((sim_cia) 0)
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#endif
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/* Return the current instruction address as a number.
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Some targets treat the current instruction address as a struct
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(e.g. for delay slot handling). */
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#ifndef CIA_ADDR
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#define CIA_ADDR(cia) (cia)
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#endif
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#ifndef INVALID_INSTRUCTION_ADDRESS
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#define INVALID_INSTRUCTION_ADDRESS ((address_word)0 - 1)
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#endif
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typedef struct _sim_cpu sim_cpu;
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#include "sim-module.h"
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#include "sim-trace.h"
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#include "sim-core.h"
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#include "sim-events.h"
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#include "sim-profile.h"
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#ifdef SIM_HAVE_MODEL
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#include "sim-model.h"
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#endif
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#include "sim-io.h"
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#include "sim-engine.h"
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#include "sim-watch.h"
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#include "sim-memopt.h"
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#ifdef SIM_HAVE_BREAKPOINTS
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#include "sim-break.h"
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#endif
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#include "sim-cpu.h"
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/* Global pointer to current state while sim_resume is running.
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On a machine with lots of registers, it might be possible to reserve
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one of them for current_state. However on a machine with few registers
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current_state can't permanently live in one and indirecting through it
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will be slower [in which case one can have sim_resume set globals from
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current_state for faster access].
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If CURRENT_STATE_REG is defined, it means current_state is living in
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a global register. */
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#ifdef CURRENT_STATE_REG
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/* FIXME: wip */
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#else
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extern struct sim_state *current_state;
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#endif
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/* The simulator may provide different (and faster) definition. */
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#ifndef CURRENT_STATE
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#define CURRENT_STATE current_state
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#endif
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typedef struct {
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/* Simulator's argv[0]. */
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const char *my_name;
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#define STATE_MY_NAME(sd) ((sd)->base.my_name)
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/* Who opened the simulator. */
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SIM_OPEN_KIND open_kind;
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#define STATE_OPEN_KIND(sd) ((sd)->base.open_kind)
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/* The host callbacks. */
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struct host_callback_struct *callback;
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#define STATE_CALLBACK(sd) ((sd)->base.callback)
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/* The type of simulation environment (user/operating). */
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enum sim_environment environment;
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#define STATE_ENVIRONMENT(sd) ((sd)->base.environment)
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#if 0 /* FIXME: Not ready yet. */
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/* Stuff defined in sim-config.h. */
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struct sim_config config;
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#define STATE_CONFIG(sd) ((sd)->base.config)
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#endif
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/* List of installed module `init' handlers. */
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struct module_list *modules;
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#define STATE_MODULES(sd) ((sd)->base.modules)
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/* Supported options. */
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struct option_list *options;
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#define STATE_OPTIONS(sd) ((sd)->base.options)
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/* Non-zero if -v specified. */
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int verbose_p;
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#define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p)
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/* Non cpu-specific trace data. See sim-trace.h. */
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TRACE_DATA trace_data;
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#define STATE_TRACE_DATA(sd) (& (sd)->base.trace_data)
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/* If non NULL, the BFD architecture specified on the command line */
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const struct bfd_arch_info *architecture;
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#define STATE_ARCHITECTURE(sd) ((sd)->base.architecture)
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/* If non NULL, the bfd target specified on the command line */
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const char *target;
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#define STATE_TARGET(sd) ((sd)->base.target)
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/* In standalone simulator, this is the program's arguments passed
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on the command line. */
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char **prog_argv;
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#define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv)
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/* The program's bfd. */
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struct _bfd *prog_bfd;
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#define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd)
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/* Symbol table for prog_bfd */
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struct symbol_cache_entry **prog_syms;
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#define STATE_PROG_SYMS(sd) ((sd)->base.prog_syms)
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/* The program's text section. */
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struct sec *text_section;
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/* Starting and ending text section addresses from the bfd. */
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SIM_ADDR text_start, text_end;
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#define STATE_TEXT_SECTION(sd) ((sd)->base.text_section)
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#define STATE_TEXT_START(sd) ((sd)->base.text_start)
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#define STATE_TEXT_END(sd) ((sd)->base.text_end)
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/* Start address, set when the program is loaded from the bfd. */
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SIM_ADDR start_addr;
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#define STATE_START_ADDR(sd) ((sd)->base.start_addr)
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/* Size of the simulator's cache, if any.
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This is not the target's cache. It is the cache the simulator uses
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to process instructions. */
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unsigned int scache_size;
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#define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size)
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/* FIXME: Move to top level sim_state struct (as some struct)? */
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#ifdef SIM_HAVE_FLATMEM
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unsigned int mem_size;
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#define STATE_MEM_SIZE(sd) ((sd)->base.mem_size)
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unsigned int mem_base;
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#define STATE_MEM_BASE(sd) ((sd)->base.mem_base)
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unsigned char *memory;
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#define STATE_MEMORY(sd) ((sd)->base.memory)
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#endif
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/* core memory bus */
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#define STATE_CORE(sd) (&(sd)->base.core)
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sim_core core;
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/* Record of memory sections added via the memory-options interface. */
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#define STATE_MEMOPT(sd) ((sd)->base.memopt)
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sim_memopt *memopt;
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/* event handler */
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#define STATE_EVENTS(sd) (&(sd)->base.events)
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sim_events events;
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/* generic halt/resume engine */
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sim_engine engine;
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#define STATE_ENGINE(sd) (&(sd)->base.engine)
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/* generic watchpoint support */
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sim_watchpoints watchpoints;
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#define STATE_WATCHPOINTS(sd) (&(sd)->base.watchpoints)
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/* Pointer to list of breakpoints */
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struct sim_breakpoint *breakpoints;
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#define STATE_BREAKPOINTS(sd) ((sd)->base.breakpoints)
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#if WITH_HW
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struct sim_hw *hw;
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#define STATE_HW(sd) ((sd)->base.hw)
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#endif
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/* Marker for those wanting to do sanity checks.
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This should remain the last member of this struct to help catch
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miscompilation errors. */
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int magic;
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#define SIM_MAGIC_NUMBER 0x4242
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#define STATE_MAGIC(sd) ((sd)->base.magic)
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} sim_state_base;
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/* Functions for allocating/freeing a sim_state. */
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SIM_DESC sim_state_alloc PARAMS ((SIM_OPEN_KIND kind, host_callback *callback));
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void sim_state_free PARAMS ((SIM_DESC));
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#endif /* SIM_BASE_H */
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