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4106101c44
Some early revisions of the Cortex-A53 have an erratum (843419). The details of the erratum are quite complex and involve dynamic conditions. For the purposes of the workaround we have simplified the static conditions to an ADRP in the last two instructions of a 4KByte page, followed within four instructions by a load/store dependent on the ADRP. This patch adds support to conservatively scan for and workaround Cortex A53 erratum 843419. There are two different workaround strategies used. The first is to rewrite ADRP instructions which form part of an erratum sequence with an ADR instruction. In situations where the ADR provides insufficient offset the dependent load or store instruction from the sequence is moved to a stub section and branches are inserted from the original sequence to the relocated instruction and back again. Stub section sizes are rounded up to a multiple of 4096 in order to ensure that the act of inserting work around stubs does not create more errata sequences. Workaround stubs are always inserted into the stub section associated with the input section containing the erratum sequence. This ensures that the fully relocated form of the veneered load store instruction is available at the point in time when the stub section is written.
70 lines
2.3 KiB
Makefile
70 lines
2.3 KiB
Makefile
#source: erratum843419.s
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#as:
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#ld: --fix-cortex-a53-835769 --fix-cortex-a53-843419 -e0 --section-start .e843419=0x20000000 --section-start .e835769=0x3000000 -Ttext=0x400000 -Tdata=0x40000000
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#objdump: -dr
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#...
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Disassembly of section .e843419:
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0000000020000000 <e843419>:
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20000000: d10043ff sub sp, sp, #0x10
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20000004: d28001a7 mov x7, #0xd // #13
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20000008: b9000fe7 str w7, \[sp,#12\]
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2000000c: 140003fb b 20000ff8 <e843419_1>
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...
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0000000020000ff8 <e843419_1>:
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20000ff8: 90100000 adrp x0, 40000000 <[_a-zA-z0-9]+>
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20000ffc: f800c007 stur x7, \[x0,#12\]
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20001000: d2800128 mov x8, #0x9 // #9
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20001004: 14000008 b 20001024 <e843419@0002_00000013_1004>
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20001008: 8b050020 add x0, x1, x5
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2000100c: b9400fe7 ldr w7, \[sp,#12\]
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20001010: 0b0700e0 add w0, w7, w7
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20001014: 910043ff add sp, sp, #0x10
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20001018: 14000005 b 2000102c <__e835769_veneer>
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2000101c: d65f03c0 ret
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20001020: 14000400 b 20002020 <__e835769_veneer\+0xff4>
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0000000020001024 <e843419@0002_00000013_1004>:
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20001024: f9000008 str x8, \[x0\]
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20001028: 17fffff8 b 20001008 <e843419_1\+0x10>
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000000002000102c <__e835769_veneer>:
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2000102c: f0f17ff0 adrp x16, 3000000 <e835769>
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20001030: 91000210 add x16, x16, #0x0
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20001034: d61f0200 br x16
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...
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Disassembly of section .e835769:
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0000000003000000 <e835769>:
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3000000: b8408c87 ldr w7, \[x4,#8\]!
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3000004: 1b017c06 mul w6, w0, w1
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3000008: f9400084 ldr x4, \[x4\]
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300000c: 14000004 b 300001c <__erratum_835769_veneer_0>
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3000010: aa0503e0 mov x0, x5
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3000014: d65f03c0 ret
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3000018: 14000400 b 3001018 <__erratum_835769_veneer_0\+0xffc>
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000000000300001c <__erratum_835769_veneer_0>:
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300001c: 9b031845 madd x5, x2, x3, x6
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3000020: 17fffffc b 3000010 <e835769\+0x10>
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...
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Disassembly of section .text:
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0000000000400000 <main>:
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400000: d10043ff sub sp, sp, #0x10
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400004: d28001a7 mov x7, #0xd // #13
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400008: b9000fe7 str w7, \[sp,#12\]
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40000c: 14000003 b 400018 <__e843419_veneer>
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400010: d65f03c0 ret
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400014: 14000400 b 401014 <__e843419_veneer\+0xffc>
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0000000000400018 <__e843419_veneer>:
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400018: 900fe010 adrp x16, 20000000 <e843419>
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40001c: 91000210 add x16, x16, #0x0
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400020: d61f0200 br x16
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...
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