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564 lines
18 KiB
C
564 lines
18 KiB
C
/* Copyright (C) 1998, Cygnus Solutions
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SIM_MAIN_C
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#define SIM_MAIN_C
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#include "sim-main.h"
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#include "sim-assert.h"
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/*---------------------------------------------------------------------------*/
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/*-- simulator engine -------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Description from page A-22 of the "MIPS IV Instruction Set" manual
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(revision 3.1) */
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/* Translate a virtual address to a physical address and cache
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coherence algorithm describing the mechanism used to resolve the
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memory reference. Given the virtual address vAddr, and whether the
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reference is to Instructions ot Data (IorD), find the corresponding
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physical address (pAddr) and the cache coherence algorithm (CCA)
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used to resolve the reference. If the virtual address is in one of
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the unmapped address spaces the physical address and the CCA are
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determined directly by the virtual address. If the virtual address
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is in one of the mapped address spaces then the TLB is used to
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determine the physical address and access type; if the required
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translation is not present in the TLB or the desired access is not
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permitted the function fails and an exception is taken.
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NOTE: Normally (RAW == 0), when address translation fails, this
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function raises an exception and does not return. */
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INLINE_SIM_MAIN
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(int)
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address_translation (SIM_DESC sd,
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sim_cpu * cpu,
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address_word cia,
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address_word vAddr,
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int IorD,
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int LorS,
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address_word * pAddr,
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int *CCA,
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int raw)
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{
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int res = -1; /* TRUE : Assume good return */
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#ifdef DEBUG
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sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
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#endif
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/* Check that the address is valid for this memory model */
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/* For a simple (flat) memory model, we simply pass virtual
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addressess through (mostly) unchanged. */
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vAddr &= 0xFFFFFFFF;
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*pAddr = vAddr; /* default for isTARGET */
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*CCA = Uncached; /* not used for isHOST */
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return (res);
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}
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/* Description from page A-23 of the "MIPS IV Instruction Set" manual
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(revision 3.1) */
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/* Prefetch data from memory. Prefetch is an advisory instruction for
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which an implementation specific action is taken. The action taken
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may increase performance, but must not change the meaning of the
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program, or alter architecturally-visible state. */
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INLINE_SIM_MAIN (void)
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prefetch (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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int CCA,
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address_word pAddr,
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address_word vAddr,
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int DATA,
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int hint)
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{
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#ifdef DEBUG
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sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
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#endif /* DEBUG */
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/* For our simple memory model we do nothing */
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return;
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}
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/* Description from page A-22 of the "MIPS IV Instruction Set" manual
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(revision 3.1) */
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/* Load a value from memory. Use the cache and main memory as
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specified in the Cache Coherence Algorithm (CCA) and the sort of
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access (IorD) to find the contents of AccessLength memory bytes
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starting at physical location pAddr. The data is returned in the
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fixed width naturally-aligned memory element (MemElem). The
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low-order two (or three) bits of the address and the AccessLength
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indicate which of the bytes within MemElem needs to be given to the
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processor. If the memory access type of the reference is uncached
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then only the referenced bytes are read from memory and valid
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within the memory element. If the access type is cached, and the
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data is not present in cache, an implementation specific size and
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alignment block of memory is read and loaded into the cache to
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satisfy a load reference. At a minimum, the block is the entire
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memory element. */
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INLINE_SIM_MAIN (void)
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load_memory (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia,
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uword64* memvalp,
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uword64* memval1p,
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int CCA,
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unsigned int AccessLength,
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address_word pAddr,
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address_word vAddr,
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int IorD)
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{
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uword64 value = 0;
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uword64 value1 = 0;
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#ifdef DEBUG
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sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
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#endif /* DEBUG */
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#if defined(WARN_MEM)
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if (CCA != uncached)
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sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
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#endif /* WARN_MEM */
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if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
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{
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/* In reality this should be a Bus Error */
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sim_io_error (SD, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
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AccessLength,
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(LOADDRMASK + 1) << 3,
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pr_addr (pAddr));
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}
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#if defined(TRACE)
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dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
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#endif /* TRACE */
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/* Read the specified number of bytes from memory. Adjust for
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host/target byte ordering/ Align the least significant byte
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read. */
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switch (AccessLength)
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{
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case AccessLength_QUADWORD:
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{
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unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
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value1 = VH8_16 (val);
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value = VL8_16 (val);
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break;
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}
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case AccessLength_DOUBLEWORD:
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value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_SEPTIBYTE:
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value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_SEXTIBYTE:
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value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_QUINTIBYTE:
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value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_WORD:
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value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_TRIPLEBYTE:
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value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_HALFWORD:
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value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
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break;
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case AccessLength_BYTE:
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value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
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break;
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default:
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abort ();
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}
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#ifdef DEBUG
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printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
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(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
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#endif /* DEBUG */
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/* See also store_memory. Position data in correct byte lanes. */
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if (AccessLength <= LOADDRMASK)
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{
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if (BigEndianMem)
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/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
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shifted to the most significant byte position. */
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value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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else
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/* For little endian target, byte (pAddr&LOADDRMASK == 0)
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is already in the correct postition. */
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value <<= ((pAddr & LOADDRMASK) * 8);
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}
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#ifdef DEBUG
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printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
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pr_uword64(value1),pr_uword64(value));
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#endif /* DEBUG */
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*memvalp = value;
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if (memval1p) *memval1p = value1;
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}
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/* Description from page A-23 of the "MIPS IV Instruction Set" manual
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(revision 3.1) */
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/* Store a value to memory. The specified data is stored into the
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physical location pAddr using the memory hierarchy (data caches and
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main memory) as specified by the Cache Coherence Algorithm
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(CCA). The MemElem contains the data for an aligned, fixed-width
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memory element (word for 32-bit processors, doubleword for 64-bit
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processors), though only the bytes that will actually be stored to
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memory need to be valid. The low-order two (or three) bits of pAddr
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and the AccessLength field indicates which of the bytes within the
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MemElem data should actually be stored; only these bytes in memory
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will be changed. */
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INLINE_SIM_MAIN (void)
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store_memory (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia,
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int CCA,
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unsigned int AccessLength,
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uword64 MemElem,
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uword64 MemElem1, /* High order 64 bits */
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address_word pAddr,
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address_word vAddr)
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{
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#ifdef DEBUG
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sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
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#endif /* DEBUG */
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#if defined(WARN_MEM)
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if (CCA != uncached)
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sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
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#endif /* WARN_MEM */
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if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
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sim_io_error (SD, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
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AccessLength,
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(LOADDRMASK + 1) << 3,
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pr_addr(pAddr));
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#if defined(TRACE)
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dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
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#endif /* TRACE */
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#ifdef DEBUG
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printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
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#endif /* DEBUG */
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/* See also load_memory. Position data in correct byte lanes. */
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if (AccessLength <= LOADDRMASK)
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{
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if (BigEndianMem)
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/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
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shifted to the most significant byte position. */
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MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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else
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/* For little endian target, byte (pAddr&LOADDRMASK == 0)
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is already in the correct postition. */
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MemElem >>= ((pAddr & LOADDRMASK) * 8);
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}
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#ifdef DEBUG
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printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
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#endif /* DEBUG */
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switch (AccessLength)
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{
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case AccessLength_QUADWORD:
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{
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unsigned_16 val = U16_8 (MemElem1, MemElem);
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sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
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break;
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}
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case AccessLength_DOUBLEWORD:
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sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_SEPTIBYTE:
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sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_SEXTIBYTE:
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sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_QUINTIBYTE:
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sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_WORD:
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sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_TRIPLEBYTE:
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sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_HALFWORD:
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sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
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break;
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case AccessLength_BYTE:
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sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
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break;
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default:
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abort ();
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}
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return;
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}
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INLINE_SIM_MAIN (unsigned32)
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ifetch32 (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia,
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address_word vaddr)
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{
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/* Copy the action of the LW instruction */
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address_word mask = LOADDRMASK;
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address_word access = AccessLength_WORD;
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address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
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address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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if ((vaddr & access) != 0)
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SignalExceptionInstructionFetch ();
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AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
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byte = ((vaddr & mask) ^ bigendiancpu);
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return (memval >> (8 * byte));
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}
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INLINE_SIM_MAIN (unsigned16)
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ifetch16 (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia,
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address_word vaddr)
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{
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/* Copy the action of the LH instruction */
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address_word mask = LOADDRMASK;
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address_word access = AccessLength_HALFWORD;
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address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
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address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
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unsigned int byte;
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address_word paddr;
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int uncached;
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unsigned64 memval;
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if ((vaddr & access) != 0)
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SignalExceptionInstructionFetch ();
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AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
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byte = ((vaddr & mask) ^ bigendiancpu);
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return (memval >> (8 * byte));
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}
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/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
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/* Order loads and stores to synchronise shared memory. Perform the
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action necessary to make the effects of groups of synchronizable
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loads and stores indicated by stype occur in the same order for all
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processors. */
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INLINE_SIM_MAIN (void)
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sync_operation (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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int stype)
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{
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#ifdef DEBUG
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sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
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#endif /* DEBUG */
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return;
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}
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INLINE_SIM_MAIN (void)
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cache_op (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia,
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int op,
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address_word pAddr,
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address_word vAddr,
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unsigned int instruction)
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{
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#if 1 /* stop warning message being displayed (we should really just remove the code) */
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static int icache_warning = 1;
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static int dcache_warning = 1;
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#else
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static int icache_warning = 0;
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static int dcache_warning = 0;
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#endif
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/* If CP0 is not useable (User or Supervisor mode) and the CP0
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enable bit in the Status Register is clear - a coprocessor
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unusable exception is taken. */
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#if 0
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sim_io_printf(SD,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
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#endif
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switch (op & 0x3) {
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case 0: /* instruction cache */
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switch (op >> 2) {
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case 0: /* Index Invalidate */
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case 1: /* Index Load Tag */
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case 2: /* Index Store Tag */
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case 4: /* Hit Invalidate */
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case 5: /* Fill */
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case 6: /* Hit Writeback */
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if (!icache_warning)
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{
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sim_io_eprintf(SD,"Instruction CACHE operation %d to be coded\n",(op >> 2));
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icache_warning = 1;
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}
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break;
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default:
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SignalException(ReservedInstruction,instruction);
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break;
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}
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break;
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case 1: /* data cache */
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case 3: /* secondary data cache */
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switch (op >> 2) {
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case 0: /* Index Writeback Invalidate */
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case 1: /* Index Load Tag */
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case 2: /* Index Store Tag */
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case 3: /* Create Dirty */
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case 4: /* Hit Invalidate */
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case 5: /* Hit Writeback Invalidate */
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case 6: /* Hit Writeback */
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if (!dcache_warning)
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{
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sim_io_eprintf(SD,"Data CACHE operation %d to be coded\n",(op >> 2));
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dcache_warning = 1;
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}
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break;
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default:
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SignalException(ReservedInstruction,instruction);
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break;
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}
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break;
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default: /* unrecognised cache ID */
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SignalException(ReservedInstruction,instruction);
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break;
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}
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return;
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}
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INLINE_SIM_MAIN (void)
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pending_tick (SIM_DESC SD,
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sim_cpu *CPU,
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address_word cia)
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{
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if (PENDING_TRACE)
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sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL);
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if (PENDING_OUT != PENDING_IN)
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{
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int loop;
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int index = PENDING_OUT;
|
|
int total = PENDING_TOTAL;
|
|
if (PENDING_TOTAL == 0)
|
|
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
|
|
for (loop = 0, index = PENDING_OUT;
|
|
(loop < total);
|
|
loop++, index = (index + 1) % PSLOTS)
|
|
{
|
|
if (PENDING_SLOT_DEST[index] != NULL)
|
|
{
|
|
PENDING_SLOT_DELAY[index] -= 1;
|
|
if (PENDING_SLOT_DELAY[index] == 0)
|
|
{
|
|
if (PENDING_TRACE)
|
|
sim_io_eprintf (SD, "PENDING_DRAIN - drained - index %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
|
|
index,
|
|
(unsigned long) PENDING_SLOT_DEST[index],
|
|
PENDING_SLOT_BIT[index],
|
|
(unsigned long) PENDING_SLOT_VALUE[index],
|
|
PENDING_SLOT_SIZE[index]);
|
|
if (PENDING_SLOT_BIT[index] >= 0)
|
|
switch (PENDING_SLOT_SIZE[index])
|
|
{
|
|
case 4:
|
|
if (PENDING_SLOT_VALUE[index])
|
|
*(unsigned32*)PENDING_SLOT_DEST[index] |=
|
|
BIT32 (PENDING_SLOT_BIT[index]);
|
|
else
|
|
*(unsigned32*)PENDING_SLOT_DEST[index] &=
|
|
BIT32 (PENDING_SLOT_BIT[index]);
|
|
break;
|
|
case 8:
|
|
if (PENDING_SLOT_VALUE[index])
|
|
*(unsigned64*)PENDING_SLOT_DEST[index] |=
|
|
BIT64 (PENDING_SLOT_BIT[index]);
|
|
else
|
|
*(unsigned64*)PENDING_SLOT_DEST[index] &=
|
|
BIT64 (PENDING_SLOT_BIT[index]);
|
|
break;
|
|
}
|
|
else
|
|
switch (PENDING_SLOT_SIZE[index])
|
|
{
|
|
case 4:
|
|
*(unsigned32*)PENDING_SLOT_DEST[index] =
|
|
PENDING_SLOT_VALUE[index];
|
|
break;
|
|
case 8:
|
|
*(unsigned64*)PENDING_SLOT_DEST[index] =
|
|
PENDING_SLOT_VALUE[index];
|
|
break;
|
|
}
|
|
if (PENDING_OUT == index)
|
|
{
|
|
PENDING_SLOT_DEST[index] = NULL;
|
|
PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
|
|
PENDING_TOTAL--;
|
|
}
|
|
}
|
|
else if (PENDING_TRACE && PENDING_SLOT_DELAY[index] > 0)
|
|
sim_io_eprintf (SD, "PENDING_DRAIN - queued - index %d, delay %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
|
|
index, PENDING_SLOT_DELAY[index],
|
|
(unsigned long) PENDING_SLOT_DEST[index],
|
|
PENDING_SLOT_BIT[index],
|
|
(unsigned long) PENDING_SLOT_VALUE[index],
|
|
PENDING_SLOT_SIZE[index]);
|
|
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
#endif
|