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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
177 lines
4.4 KiB
C
177 lines
4.4 KiB
C
/* Disassembler structures definitions for the ARC.
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Copyright (C) 1994-2024 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef ARCDIS_H
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#define ARCDIS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum arc_ldst_writeback_mode
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{
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ARC_WRITEBACK_NO = 0,
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ARC_WRITEBACK_AW = 1,
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ARC_WRITEBACK_A = ARC_WRITEBACK_AW,
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ARC_WRITEBACK_AB = 2,
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ARC_WRITEBACK_AS = 3,
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};
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enum arc_ldst_data_size
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{
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ARC_SCALING_NONE = 4,
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ARC_SCALING_B = 1,
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ARC_SCALING_H = 2,
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ARC_SCALING_D = 8,
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};
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enum arc_condition_code
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{
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ARC_CC_AL = 0x0,
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ARC_CC_RA = ARC_CC_AL,
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ARC_CC_EQ = 0x1,
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ARC_CC_Z = ARC_CC_EQ,
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ARC_CC_NE = 0x2,
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ARC_CC_NZ = ARC_CC_NE,
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ARC_CC_PL = 0x3,
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ARC_CC_P = ARC_CC_PL,
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ARC_CC_MI = 0x4,
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ARC_CC_N = ARC_CC_MI,
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ARC_CC_CS = 0x5,
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ARC_CC_C = ARC_CC_CS,
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ARC_CC_LO = ARC_CC_CS,
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ARC_CC_CC = 0x6,
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ARC_CC_NC = ARC_CC_CC,
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ARC_CC_HS = ARC_CC_CC,
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ARC_CC_VS = 0x7,
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ARC_CC_V = ARC_CC_VS,
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ARC_CC_VC = 0x8,
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ARC_CC_NV = ARC_CC_VC,
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ARC_CC_GT = 0x9,
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ARC_CC_GE = 0xA,
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ARC_CC_LT = 0xB,
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ARC_CC_LE = 0xC,
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ARC_CC_HI = 0xD,
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ARC_CC_LS = 0xE,
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ARC_CC_PNZ = 0xF,
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ARC_CC_UNDEF0 = 0x10,
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ARC_CC_UNDEF1 = 0x11,
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ARC_CC_UNDEF2 = 0x12,
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ARC_CC_UNDEF3 = 0x13,
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ARC_CC_UNDEF4 = 0x14,
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ARC_CC_UNDEF5 = 0x15,
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ARC_CC_UNDEF6 = 0x16,
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ARC_CC_UNDEF7 = 0x17,
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ARC_CC_UNDEF8 = 0x18,
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ARC_CC_UNDEF9 = 0x19,
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ARC_CC_UNDEFA = 0x1A,
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ARC_CC_UNDEFB = 0x1B,
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ARC_CC_UNDEFC = 0x1C,
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ARC_CC_UNDEFD = 0x1D,
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ARC_CC_UNDEFE = 0x1E,
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ARC_CC_UNDEFF = 0x1F
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};
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enum arc_operand_kind
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{
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ARC_OPERAND_KIND_UNKNOWN = 0,
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ARC_OPERAND_KIND_REG,
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ARC_OPERAND_KIND_SHIMM,
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ARC_OPERAND_KIND_LIMM
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};
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struct arc_insn_operand
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{
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/* Operand value as encoded in instruction. */
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unsigned long value;
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enum arc_operand_kind kind;
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};
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/* Container for information about instruction. Provides a higher
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level access to data that is contained in struct arc_opcode. */
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struct arc_instruction
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{
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/* Address of this instruction. */
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bfd_vma address;
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/* Whether this is a valid instruction. */
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bool valid;
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insn_class_t insn_class;
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/* Length (without LIMM). */
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unsigned length;
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/* Is there a LIMM in this instruction? */
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int limm_p;
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/* Long immediate value. */
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unsigned limm_value;
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/* Is it a branch/jump instruction? */
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int is_control_flow;
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/* Whether this instruction has a delay slot. */
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int has_delay_slot;
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/* Value of condition code field. */
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enum arc_condition_code condition_code;
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/* Load/store writeback mode. */
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enum arc_ldst_writeback_mode writeback_mode;
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/* Load/store data size. */
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enum arc_ldst_data_size data_size_mode;
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/* Amount of operands in instruction. Note that amount of operands
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reported by opcodes disassembler can be different from the one
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encoded in the instruction. Notable case is "ld a,[b,offset]",
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when offset == 0. In this case opcodes disassembler presents
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this instruction as "ld a,[b]", hence there are *two* operands,
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not three. OPERANDS_COUNT and OPERANDS contain only those
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explicit operands, hence it is up to invoker to handle the case
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described above based on instruction opcodes. Another notable
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thing is that in opcodes disassembler representation square
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brackets (`[' and `]') are so called fake-operands - they are in
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the list of operands, but do not have any value of they own.
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Those "operands" are not present in this array. */
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struct arc_insn_operand operands[MAX_INSN_ARGS];
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unsigned int operands_count;
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};
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/* Fill INSN with data about instruction at specified ADDR. */
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void arc_insn_decode (bfd_vma addr,
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struct disassemble_info *di,
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disassembler_ftype func,
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struct arc_instruction *insn);
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#ifdef __cplusplus
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}
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#endif
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#endif
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