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fa8b7c2128
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file.
109 lines
2.0 KiB
Plaintext
109 lines
2.0 KiB
Plaintext
dnl Note that this file is intended to be included at the m4 level and not
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dnl the shell level, so use sinclude(...) to pull it in.
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# WHEN ADDING ENTRIES TO THIS MATRIX:
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# Make sure that the left side always has two dashes. Otherwise you
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# can get spurious matches. Even for unambiguous cases, do this as a
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# convention, else the table becomes a real mess to understand and
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# maintain.
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dnl glue to avoid code duplication at top level
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m4_ifndef([SIM_ARCH], [AC_DEFUN([SIM_ARCH],[sim_arch=$1])])
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sim_igen=no
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sim_arch=
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case "${target}" in
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aarch64*-*-*)
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SIM_ARCH(aarch64)
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;;
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arm*-*-*)
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SIM_ARCH(arm)
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;;
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avr*-*-*)
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SIM_ARCH(avr)
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;;
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bfin-*-*)
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SIM_ARCH(bfin)
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;;
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cr16*-*-*)
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SIM_ARCH(cr16)
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;;
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cris-*-* | crisv32-*-*)
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SIM_ARCH(cris)
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;;
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d10v-*-*)
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SIM_ARCH(d10v)
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;;
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frv-*-*)
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SIM_ARCH(frv)
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;;
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h8300*-*-*)
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SIM_ARCH(h8300)
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;;
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iq2000-*-*)
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SIM_ARCH(iq2000)
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;;
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lm32-*-*)
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SIM_ARCH(lm32)
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;;
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m32c-*-*)
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SIM_ARCH(m32c)
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;;
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m32r-*-*)
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SIM_ARCH(m32r)
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;;
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m68hc11-*-*|m6811-*-*)
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SIM_ARCH(m68hc11)
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;;
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mcore-*-*)
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SIM_ARCH(mcore)
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;;
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microblaze-*-*)
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SIM_ARCH(microblaze)
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;;
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mips*-*-*)
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SIM_ARCH(mips)
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sim_igen=yes
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;;
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mn10300*-*-*)
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SIM_ARCH(mn10300)
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sim_igen=yes
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;;
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moxie-*-*)
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SIM_ARCH(moxie)
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;;
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msp430*-*-*)
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SIM_ARCH(msp430)
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;;
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or1k-*-* | or1knd-*-*)
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SIM_ARCH(or1k)
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;;
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rl78-*-*)
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SIM_ARCH(rl78)
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;;
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rx-*-*)
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SIM_ARCH(rx)
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;;
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sh64*-*-*)
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SIM_ARCH(sh64)
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;;
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sh*-*-*)
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SIM_ARCH(sh)
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;;
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sparc-*-rtems*|sparc-*-elf*)
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SIM_ARCH(erc32)
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;;
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powerpc*-*-*)
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SIM_ARCH(ppc)
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;;
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ft32-*-*)
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SIM_ARCH(ft32)
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;;
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v850*-*-*)
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SIM_ARCH(v850)
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sim_igen=yes
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;;
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esac
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AC_SUBST(sim_arch)
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