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This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask. |
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| .. | ||
| aarch64.h | ||
| alpha.h | ||
| arc-attrs.h | ||
| arc-func.h | ||
| arc.h | ||
| arm.h | ||
| avr.h | ||
| bfin.h | ||
| cgen.h | ||
| ChangeLog-0415 | ||
| ChangeLog-9103 | ||
| convex.h | ||
| cr16.h | ||
| cris.h | ||
| crx.h | ||
| csky.h | ||
| d10v.h | ||
| d30v.h | ||
| dlx.h | ||
| ft32.h | ||
| h8300.h | ||
| hppa.h | ||
| i386.h | ||
| ia64.h | ||
| loongarch.h | ||
| m68hc11.h | ||
| m68k.h | ||
| metag.h | ||
| mips.h | ||
| mmix.h | ||
| mn10200.h | ||
| mn10300.h | ||
| moxie.h | ||
| msp430-decode.h | ||
| msp430.h | ||
| nds32.h | ||
| nfp.h | ||
| nios2.h | ||
| nios2r1.h | ||
| nios2r2.h | ||
| np1.h | ||
| ns32k.h | ||
| pdp11.h | ||
| pj.h | ||
| pn.h | ||
| ppc.h | ||
| pru.h | ||
| pyr.h | ||
| riscv-opc.h | ||
| riscv.h | ||
| rl78.h | ||
| rx.h | ||
| s12z.h | ||
| s390.h | ||
| score-datadep.h | ||
| score-inst.h | ||
| sparc.h | ||
| spu-insns.h | ||
| spu.h | ||
| tic4x.h | ||
| tic6x-control-registers.h | ||
| tic6x-insn-formats.h | ||
| tic6x-opcode-table.h | ||
| tic6x.h | ||
| tic30.h | ||
| tic54x.h | ||
| tilegx.h | ||
| tilepro.h | ||
| v850.h | ||
| vax.h | ||
| visium.h | ||
| wasm.h | ||
| xgate.h | ||