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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
127 lines
2.5 KiB
ArmAsm
127 lines
2.5 KiB
ArmAsm
# Hitachi H8 testcase 'cmp.w'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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start
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.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
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cmp_w_imm3: ;
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; cmp.w #xx:3,Rd ; Immediate 3-bit operand
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mov.w #5, r0
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cmp.w #5, r0
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beq eq3
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fail
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eq3:
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cmp.w #6, r0
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blt lt3
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fail
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lt3:
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cmp.w #4, r0
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bgt gt3
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fail
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gt3:
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a50005 er0 ; er0 unchanged
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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cmp_w_imm16: ; cmp.w immediate not available in h8300 mode.
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; cmp.w #xx:16,Rd
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cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
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beq eqi
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fail
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eqi: cmp.w #0xa5a6, r0
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blt lti
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fail
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lti: cmp.w #0xa5a4, r0
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bgt gti
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fail
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gti:
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a5 r0 ; r0 unchanged
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate
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set_grs_a5a5
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;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff).
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sub.w r0, r0
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cmp.w #0x8001, r0
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bls ltz
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fail
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ltz: test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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cmp_w_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; cmp.w Rs,Rd
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mov.w #0xa5a5, r1
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cmp.w r1, r0 ; Register operand
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beq eqr
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fail
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eqr: mov.w #0xa5a6, r1
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cmp.w r1, r0
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blt ltr
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fail
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ltr: mov.w #0xa5a4, r1
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cmp.w r1, r0
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bgt gtr
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fail
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gtr:
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a5 r0 ; r0 unchanged.
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test_h_gr16 0xa5a4 r1 ; r1 unchanged.
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
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test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
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.endif
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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pass
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exit 0
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