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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
229 lines
5.0 KiB
Plaintext
229 lines
5.0 KiB
Plaintext
# frv testcase for nfmuls $FRi,$FRj,$FRk
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# mach: fr500 fr550 frv
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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.global nfmuls
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nfmuls:
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nfmuls fr16,fr4,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr8,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr12,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr16,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr20,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr24,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr32,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr36,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr40,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr44,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr16,fr48,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr4,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr8,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr12,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr16,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr20,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr24,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr32,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr36,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr40,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr44,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr20,fr48,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr0,fr1
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test_fr_fr fr1,fr0
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr4,fr1
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test_fr_fr fr1,fr4
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr8,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr12,fr1
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test_fr_fr fr1,fr12
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr16,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr20,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr24,fr1
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test_fr_fr fr1,fr24
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr28,fr1
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test_fr_fr fr1,fr28
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr32,fr1
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test_fr_fr fr1,fr32
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr36,fr1
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test_fr_fr fr1,fr36
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr40,fr1
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test_fr_fr fr1,fr40
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr44,fr1
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test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr48,fr1
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test_fr_fr fr1,fr48
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr52,fr1
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test_fr_fr fr1,fr52
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr28,fr8,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr8,fr28,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr32,fr36,fr1
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test_fr_fr fr1,fr40
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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; try to cause exceptions
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nfmuls fr48,fr32,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr52,fr28,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr56,fr28,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfmuls fr60,fr28,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 2,fner1
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test_spr_immed 0,fner0
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pass
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