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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
1550 lines
42 KiB
Plaintext
1550 lines
42 KiB
Plaintext
# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2
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# mach: frv
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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load_float_constants1
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.global nfdcmps
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nfdcmps:
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set_fcc 0x7,0 ; Set mask opposite of expected
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set_fcc 0x7,1 ; Set mask opposite of expected
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nfdcmps fr0,fr0,fcc0
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test_fcc 0x8,0
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test_fcc 0x8,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr4,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr8,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr12,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr16,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr20,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr24,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr28,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr32,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr36,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr40,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr44,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr48,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr0,fr52,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr0,fr56,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr0,fr60,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr4,fr0,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0x7,0 ; Set mask opposite of expected
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set_fcc 0x7,1 ; Set mask opposite of expected
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nfdcmps fr4,fr4,fcc0
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test_fcc 0x8,0
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test_fcc 0x8,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr8,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr12,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr16,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr20,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr24,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr28,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr32,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr36,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr40,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr44,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr48,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr4,fr52,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr4,fr56,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr4,fr60,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr8,fr0,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr8,fr4,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0x7,0 ; Set mask opposite of expected
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set_fcc 0x7,1 ; Set mask opposite of expected
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nfdcmps fr8,fr8,fcc0
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test_fcc 0x8,0
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test_fcc 0x8,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr12,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr16,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr20,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr24,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr28,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr32,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr36,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr40,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr44,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr48,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr8,fr52,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr8,fr56,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xe,0 ; Set mask opposite of expected
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set_fcc 0xe,1 ; Set mask opposite of expected
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nfdcmps fr8,fr60,fcc0
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test_fcc 0x1,0
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test_fcc 0x1,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr12,fr0,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr12,fr4,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xd,0 ; Set mask opposite of expected
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set_fcc 0xd,1 ; Set mask opposite of expected
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nfdcmps fr12,fr8,fcc0
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test_fcc 0x2,0
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test_fcc 0x2,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0x7,0 ; Set mask opposite of expected
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set_fcc 0x7,1 ; Set mask opposite of expected
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nfdcmps fr12,fr12,fcc0
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test_fcc 0x8,0
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test_fcc 0x8,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr12,fr16,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr12,fr20,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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set_fcc 0xb,0 ; Set mask opposite of expected
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set_fcc 0xb,1 ; Set mask opposite of expected
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nfdcmps fr12,fr24,fcc0
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test_fcc 0x4,0
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test_fcc 0x4,1
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test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr28,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr32,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr36,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr40,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr44,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr48,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr12,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr16,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr20,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr24,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr28,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr32,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr36,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr40,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr44,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr48,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr16,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr16,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr20,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr24,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr28,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr32,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr36,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr40,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr44,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr48,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr20,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr16,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr20,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr24,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr28,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr32,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr36,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr40,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr44,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr48,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr24,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr16,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr20,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr24,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr28,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr32,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr36,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr40,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr44,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr48,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr28,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr16,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr20,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr24,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr28,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr32,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr36,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr40,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr44,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr48,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
|
set_fcc 0xb,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr52,fcc0
|
|
test_fcc 0x4,0
|
|
test_fcc 0x4,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr48,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr0,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr4,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr8,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr12,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr16,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr20,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr24,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr28,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr32,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr36,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr40,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr44,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
|
set_fcc 0xd,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr48,fcc0
|
|
test_fcc 0x2,0
|
|
test_fcc 0x2,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
|
set_fcc 0x7,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr52,fcc0
|
|
test_fcc 0x8,0
|
|
test_fcc 0x8,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr52,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr0,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr4,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr8,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr12,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr16,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr20,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr24,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr28,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr32,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr36,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr40,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr44,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr48,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr52,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr56,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr0,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr4,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr8,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr12,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr16,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr20,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr24,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr28,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr32,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr36,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr40,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr44,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr48,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr52,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr56,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
|
set_fcc 0xe,1 ; Set mask opposite of expected
|
|
nfdcmps fr60,fr60,fcc0
|
|
test_fcc 0x1,0
|
|
test_fcc 0x1,1
|
|
test_spr_immed 0,fner1
|
|
test_spr_immed 0,fner0
|
|
|
|
pass
|