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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
127 lines
3.4 KiB
Plaintext
127 lines
3.4 KiB
Plaintext
# frv testcase for cand $GRi,$GRj,$GRk
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# mach: all
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.include "testutils.inc"
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start
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.global cand
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cand:
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set_spr_immed 0x1b1b,cccr
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc0,1
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test_icc 1 0 1 1 icc0
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test_gr_immed 0,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc0,1
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test_icc 0 1 0 0 icc0
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test_gr_limmed 0xaaaa,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc4,1
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test_icc 1 1 0 1 icc0
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test_gr_limmed 0x0000,0xaaaa,gr8
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc0,0
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test_icc 1 0 1 1 icc0
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test_gr_limmed 0x5555,0x5555,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc0,0
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test_icc 0 1 0 0 icc0
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test_gr_limmed 0xffff,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,0 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc4,0
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test_icc 1 1 0 1 icc0
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test_gr_limmed 0x0000,0xffff,gr8
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc1,0
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test_icc 1 0 1 1 icc1
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test_gr_immed 0,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc1,0
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test_icc 0 1 0 0 icc1
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test_gr_limmed 0xaaaa,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc5,0
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test_icc 1 1 0 1 icc1
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test_gr_limmed 0x0000,0xaaaa,gr8
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc1,1
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test_icc 1 0 1 1 icc1
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test_gr_limmed 0x5555,0x5555,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc1,1
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test_icc 0 1 0 0 icc1
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test_gr_limmed 0xffff,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,1 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc5,1
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test_icc 1 1 0 1 icc1
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test_gr_limmed 0x0000,0xffff,gr8
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,2 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc2,0
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test_icc 1 0 1 1 icc2
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test_gr_limmed 0x5555,0x5555,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,2 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc2,0
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test_icc 0 1 0 0 icc2
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test_gr_limmed 0xffff,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,2 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc6,1
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test_icc 1 1 0 1 icc2
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test_gr_limmed 0x0000,0xffff,gr8
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set_gr_limmed 0xaaaa,0xaaaa,gr7
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set_gr_limmed 0x5555,0x5555,gr8
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set_icc 0x0b,3 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc3,0
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test_icc 1 0 1 1 icc3
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test_gr_limmed 0x5555,0x5555,gr8
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set_gr_limmed 0xffff,0x0000,gr8
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set_icc 0x04,3 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc3,0
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test_icc 0 1 0 0 icc3
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test_gr_limmed 0xffff,0x0000,gr8
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set_gr_limmed 0x0000,0xffff,gr8
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set_icc 0x0d,3 ; Set mask opposite of expected
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cand gr7,gr8,gr8,cc7,1
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test_icc 1 1 0 1 icc3
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test_gr_limmed 0x0000,0xffff,gr8
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pass
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