mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-01-12 12:16:04 +08:00
Code Issues Packages Projects Releases Wiki Activity
04381273a9
binutils-gdb/sim/example-synacor
History
Mike Frysinger 04381273a9 sim: unify debug/stdio/trace/profile build settings 
Move these options up to the common dir so we only test & export
them once across all ports.

The ppc code needs a little extra care with its trace settings as
it's not exactly the same API as the common code.  The other knobs
are the same though.
2021-06-12 20:07:57 -04:00
..
aclocal.m4 sim: unify environment build settings 2021-06-12 11:01:57 -04:00
ChangeLog sim: unify assert build settings 2021-06-12 10:58:22 -04:00
config.in sim: unify debug/stdio/trace/profile build settings 2021-06-12 20:07:57 -04:00
configure sim: unify debug/stdio/trace/profile build settings 2021-06-12 20:07:57 -04:00
configure.ac
interp.c sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
Makefile.in
README
README.arch-spec
sim-main.c sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
sim-main.h sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00

README 

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.