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40c7a7cb74
First, add nds32 audio ISA extension including opcodes and registers. Second, redesign the disassemble implement. The original disassemble decode instruction opcode using switch-case. It is hard to synchronize when adding new instructions. Therefore, the new implement reuses nds32_opcodes to dump the instructions.
298 lines
8.0 KiB
C
298 lines
8.0 KiB
C
/* NDS32-specific support for 32-bit ELF.
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Copyright (C) 2012-2014 Free Software Foundation, Inc.
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Contributed by Andes Technology Corporation.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#ifndef NDS32_ASM_H
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#define NDS32_ASM_H
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/* Constant values for assembler. */
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enum
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{
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/* Error code for assembling an instruction. */
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NASM_OK = 0,
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NASM_ERR_UNKNOWN_OP,
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NASM_ERR_SYNTAX,
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NASM_ERR_OPERAND,
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NASM_ERR_OUT_OF_RANGE,
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NASM_ERR_REG_REDUCED,
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NASM_ERR_JUNK_EOL,
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/* Results of parse_operand. */
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NASM_R_CONST,
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NASM_R_SYMBOL,
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NASM_R_ILLEGAL,
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/* Flags for open description. */
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NASM_OPEN_ARCH_V1 = 0x0,
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NASM_OPEN_ARCH_V2 = 0x1,
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NASM_OPEN_ARCH_V3 = 0x2,
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NASM_OPEN_ARCH_V3M = 0x3,
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NASM_OPEN_ARCH_MASK = 0xf,
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NASM_OPEN_REDUCED_REG = 0x10,
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/* Common attributes. */
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NASM_ATTR_ISA_V1 = 0x01,
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NASM_ATTR_ISA_V2 = 0x02,
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NASM_ATTR_ISA_V3 = 0x04,
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NASM_ATTR_ISA_V3M = 0x08,
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NASM_ATTR_ISA_ALL = 0x0f,
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/* Attributes for instructions. */
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NASM_ATTR_MAC = 0x0000100,
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NASM_ATTR_DIV = 0x0000200,
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NASM_ATTR_FPU = 0x0000400,
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NASM_ATTR_FPU_SP_EXT = 0x0000800,
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NASM_ATTR_FPU_DP_EXT = 0x0001000,
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NASM_ATTR_STR_EXT = 0x0002000,
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NASM_ATTR_PERF_EXT = 0x0004000,
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NASM_ATTR_PERF2_EXT = 0x0008000,
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NASM_ATTR_AUDIO_ISAEXT = 0x0010000,
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NASM_ATTR_IFC_EXT = 0x0020000,
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NASM_ATTR_EX9_EXT = 0x0040000,
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NASM_ATTR_FPU_FMA = 0x0080000,
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NASM_ATTR_DXREG = 0x0100000,
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NASM_ATTR_BRANCH = 0x0200000,
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NASM_ATTR_SATURATION_EXT = 0x0400000,
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NASM_ATTR_PCREL = 0x0800000,
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NASM_ATTR_GPREL = 0x1000000,
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/* Attributes for relocations. */
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NASM_ATTR_HI20 = 0x10000000,
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NASM_ATTR_LO12 = 0x20000000,
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NASM_ATTR_LO20 = 0x40000000,
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/* Attributes for registers. */
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NASM_ATTR_RDREG = 0x000100
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};
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enum
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{
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/* This is a field (operand) of just a separator char. */
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SYN_FIELD = 0x100,
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/* This operand is used for input or output. (define or use) */
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SYN_INPUT = 0x1000,
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SYN_OUTPUT = 0x2000,
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SYN_LOPT = 0x4000,
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SYN_ROPT = 0x8000,
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/* Hardware resources. */
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HW_GPR = 0,
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HW_USR,
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HW_DXR,
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HW_SR,
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HW_FSR,
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HW_FDR,
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HW_CP, /* Co-processor ID. */
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HW_CPR, /* Co-processor registers. */
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HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */
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HW_ABM, /* [ab]m? flag for LSMWZB. */
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HW_DTITON,
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HW_DTITOFF,
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HW_DPREF_ST,
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HW_CCTL_ST0,
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HW_CCTL_ST1,
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HW_CCTL_ST2,
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HW_CCTL_ST3,
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HW_CCTL_ST4,
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HW_CCTL_ST5,
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HW_CCTL_LV,
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HW_TLBOP_ST,
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HW_STANDBY_ST,
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HW_MSYNC_ST,
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HW_AEXT_IM_I,
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HW_AEXT_IM_M,
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HW_AEXT_ACC,
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HW_AEXT_ARIDX,
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HW_AEXT_ARIDX2,
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HW_AEXT_ARIDXI,
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_HW_LAST,
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/* TODO: Maybe we should add a new type to distinguish address and
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const int. Only the former allows symbols and relocations. */
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HW_INT,
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HW_UINT
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};
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/* for audio-extension. */
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enum
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{
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N32_AEXT_AMADD = 0,
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N32_AEXT_AMSUB,
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N32_AEXT_AMULT,
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N32_AEXT_AMFAR,
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N32_AEXT_AMADDS,
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N32_AEXT_AMSUBS,
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N32_AEXT_AMULTS,
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N32_AEXT_AMNEGS,
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N32_AEXT_AADDL,
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N32_AEXT_AMTARI,
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N32_AEXT_AMAWBS = 0x0c,
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N32_AEXT_AMAWTS,
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N32_AEXT_AMWBS,
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N32_AEXT_AMWTS,
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N32_AEXT_AMABBS,
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N32_AEXT_AMABTS,
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N32_AEXT_AMATBS,
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N32_AEXT_AMATTS,
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N32_AEXT_AMBBS,
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N32_AEXT_AMBTS,
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N32_AEXT_AMTBS,
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N32_AEXT_AMTTS
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};
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/* Macro for instruction attribute. */
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#define ATTR(attr) NASM_ATTR_ ## attr
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#define ATTR_NONE 0
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#define ATTR_PCREL (ATTR (PCREL) | ATTR (BRANCH))
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#define ATTR_ALL (ATTR (ISA_ALL))
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#define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1)))
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#define ATTR_V3MUP (ATTR (ISA_V3) | ATTR (ISA_V3M))
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#define ATTR_V3 (ATTR (ISA_V3))
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#define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M)))
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#define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M)))
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/* Lexical element in parsed syntax. */
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typedef int lex_t;
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/* Common header for hash entries. */
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struct nds32_hash_entry
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{
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const char *name;
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};
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typedef struct nds32_keyword
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{
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const char *name;
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int value;
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uint64_t attr;
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} keyword_t;
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typedef struct nds32_opcode
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{
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/* Opcode for the instruction. */
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const char *opcode;
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/* Human readable string of this instruction. */
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const char *instruction;
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/* Base value of this instruction. */
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uint32_t value;
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/* The byte-size of the instruction. */
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int isize;
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/* Attributes of this instruction. */
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uint64_t attr;
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/* Implicit define/use. */
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uint64_t defuse;
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/* Parsed string for assembling. */
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lex_t *syntax;
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/* Number of variant. */
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int variant;
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/* Next form of the same mnemonic. */
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struct nds32_opcode *next;
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/* TODO: Extra constrains and verification.
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For example, `mov55 $sp, $sp' is not allowed in v3. */
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} opcode_t;
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typedef struct nds32_asm_insn
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{
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/* Assembled instruction bytes. */
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uint32_t insn;
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/* The opcode structure for this instruction. */
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struct nds32_opcode *opcode;
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/* The field need special fix-up, used for relocation. */
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const struct nds32_field *field;
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/* Attributes for relocation. */
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uint64_t attr;
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/* Application-dependent data, e.g., expression. */
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void *info;
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/* Input/output registers. */
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uint64_t defuse;
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} nds32_asm_insn_t;
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typedef struct nds32_asm_desc
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{
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/* The callback provided by assembler user for parse an operand,
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e.g., parse integer. */
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int (*parse_operand) (struct nds32_asm_desc *,
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struct nds32_asm_insn *,
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char **, int64_t *);
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/* Result of assembling. */
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int result;
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/* The mach for this assembling. */
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int mach;
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int flags;
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} nds32_asm_desc_t;
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/* The field information for an operand. */
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typedef struct nds32_field
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{
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/* Name of the field. */
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const char *name;
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int bitpos;
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int bitsize;
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int shift;
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int hw_res;
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int (*parse) (struct nds32_asm_desc *,
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struct nds32_asm_insn *,
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char **, int64_t *);
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} field_t;
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extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *);
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extern void nds32_asm_init (nds32_asm_desc_t *, int);
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#define OP6(op6) (N32_OP6_ ## op6 << 25)
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#define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub)
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#define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub)
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#define JREG_RET (1 << 5)
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#define JREG_IFC (1 << 6)
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#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
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#define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub)
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#define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub)
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#define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub)
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#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
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#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
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#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12))
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#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
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#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
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| (N32_FPU_FS1_F2OP_ ## sub << 10))
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#define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
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#define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
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#define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
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| (N32_FPU_FD1_F2OP_ ## sub << 10))
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#define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
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#define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
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#define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
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| (N32_FPU_MFCP_XR_ ## sub << 10))
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#define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
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#define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
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| (N32_FPU_MTCP_XR_ ## sub << 10))
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#define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub)
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#define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7)
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#define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20))
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#endif
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