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This commits the result of running gdb/copyright.py as per our Start
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gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
94 lines
3.4 KiB
C
94 lines
3.4 KiB
C
/* OpenRISC simulator support code header
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef OR1K_SIM_H
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#define OR1K_SIM_H
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#include "symcat.h"
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/* GDB register numbers. */
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#define PPC_REGNUM 32
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#define PC_REGNUM 33
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#define SR_REGNUM 34
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/* Misc. profile data. */
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typedef struct
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{
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} OR1K_MISC_PROFILE;
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/* Nop codes used in nop simulation. */
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#define NOP_NOP 0x0
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#define NOP_EXIT 0x1
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#define NOP_REPORT 0x2
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#define NOP_PUTC 0x4
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#define NOP_CNT_RESET 0x5
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#define NOP_GET_TICKS 0x6
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#define NOP_GET_PS 0x7
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#define NOP_TRACE_ON 0x8
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#define NOP_TRACE_OFF 0x9
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#define NOP_RANDOM 0xa
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#define NOP_OR1KSIM 0xb
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#define NOP_EXIT_SILENT 0xc
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#define NUM_SPR 0x20000
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#define SPR_GROUP_SHIFT 11
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#define SPR_GROUP_FIRST(group) (((UWI) SPR_GROUP_##group) << SPR_GROUP_SHIFT)
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#define SPR_ADDR(group,index) \
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(SPR_GROUP_FIRST(group) | ((UWI) SPR_INDEX_##group##_##index))
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/* Define word getters and setter helpers based on those from
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sim/common/cgen-mem.h. */
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#define GETTWI GETTSI
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#define SETTWI SETTSI
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void or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
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const USI or1k_upr, const USI or1k_cpucfgr);
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void or1k32bf_insn_before (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
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void or1k32bf_insn_after (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
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void or1k32bf_fpu_error (CGEN_FPU* fpu, int status);
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void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum);
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void or1k32bf_rfe (sim_cpu *current_cpu);
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void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16);
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USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr);
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void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val);
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int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
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int len);
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int or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
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int len);
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int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
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int unit_num, int referenced);
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int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
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int unit_num, int referenced);
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void or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p);
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void or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles);
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USI or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr);
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void or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val);
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USI or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb,
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int lsb);
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void or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb,
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int lsb, USI val);
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USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset,
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int size);
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USI or1k32bf_ff1 (sim_cpu *current_cpu, USI val);
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USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val);
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#endif /* OR1K_SIM_H */
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