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985 lines
25 KiB
C
985 lines
25 KiB
C
/* frv trap support
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Copyright (C) 1999-2021 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define WANT_CPU frvbf
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "targ-vals.h"
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#include "cgen-engine.h"
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#include "cgen-par.h"
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#include "sim-fpu.h"
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#include "bfd.h"
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#include "libiberty.h"
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CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot;
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/* The semantic code invokes this for invalid (unrecognized) instructions. */
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
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{
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frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
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return vpc;
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}
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/* Process an address exception. */
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void
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frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
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unsigned int map, int nr_bytes, address_word addr,
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transfer_type transfer, sim_core_signals sig)
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{
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if (sig == sim_core_unaligned_signal)
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{
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if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
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|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
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frv_queue_data_access_error_interrupt (current_cpu, addr);
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else
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frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr);
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}
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frv_term (sd);
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sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr, transfer, sig);
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}
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void
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frv_sim_engine_halt_hook (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia)
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{
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int i;
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if (current_cpu != NULL)
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CPU_PC_SET (current_cpu, cia);
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/* Invalidate the insn and data caches of all cpus. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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current_cpu = STATE_CPU (sd, i);
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frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu), 0);
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frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu), 1);
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}
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frv_term (sd);
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}
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/* Read/write functions for system call interface. */
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static int
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syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, char *buf, int bytes)
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{
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1);
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return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
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}
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static int
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syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
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unsigned long taddr, const char *buf, int bytes)
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{
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SIM_DESC sd = (SIM_DESC) sc->p1;
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SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0);
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frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 1);
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return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
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}
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/* Handle TRA and TIRA insns. */
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void
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frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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host_callback *cb = STATE_CALLBACK (sd);
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USI num = ((base + offset) & 0x7f) + 0x80;
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if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
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{
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frv_queue_software_interrupt (current_cpu, num);
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return;
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}
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switch (num)
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{
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case TRAP_SYSCALL :
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{
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CB_SYSCALL s;
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CB_SYSCALL_INIT (&s);
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s.func = GET_H_GR (7);
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s.arg1 = GET_H_GR (8);
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s.arg2 = GET_H_GR (9);
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s.arg3 = GET_H_GR (10);
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if (s.func == TARGET_SYS_exit)
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{
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
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}
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s.p1 = (PTR) sd;
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s.p2 = (PTR) current_cpu;
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s.read_mem = syscall_read_mem;
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s.write_mem = syscall_write_mem;
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cb_syscall (cb, &s);
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SET_H_GR (8, s.result);
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SET_H_GR (9, s.result2);
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SET_H_GR (10, s.errcode);
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break;
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}
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case TRAP_BREAKPOINT:
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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break;
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/* Add support for dumping registers, either at fixed traps, or all
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unknown traps if configured with --enable-sim-trapdump. */
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default:
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#if !TRAPDUMP
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frv_queue_software_interrupt (current_cpu, num);
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return;
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#endif
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#ifdef TRAP_REGDUMP1
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case TRAP_REGDUMP1:
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#endif
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#ifdef TRAP_REGDUMP2
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case TRAP_REGDUMP2:
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#endif
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#if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
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{
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char buf[256];
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int i, j;
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buf[0] = 0;
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if (STATE_TEXT_SECTION (sd)
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&& pc >= STATE_TEXT_START (sd)
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&& pc < STATE_TEXT_END (sd))
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{
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const char *pc_filename = (const char *)0;
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const char *pc_function = (const char *)0;
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unsigned int pc_linenum = 0;
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if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
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STATE_TEXT_SECTION (sd),
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(struct bfd_symbol **) 0,
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pc - STATE_TEXT_START (sd),
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&pc_filename, &pc_function, &pc_linenum)
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&& (pc_function || pc_filename))
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{
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char *p = buf+2;
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buf[0] = ' ';
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buf[1] = '(';
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if (pc_function)
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{
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strcpy (p, pc_function);
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p += strlen (p);
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}
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else
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{
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char *q = (char *) strrchr (pc_filename, '/');
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strcpy (p, (q) ? q+1 : pc_filename);
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p += strlen (p);
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}
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if (pc_linenum)
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{
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sprintf (p, " line %d", pc_linenum);
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p += strlen (p);
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}
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p[0] = ')';
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p[1] = '\0';
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if ((p+1) - buf > sizeof (buf))
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abort ();
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}
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}
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sim_io_printf (sd,
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"\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
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(unsigned)pc, buf, (unsigned)base, (int)offset);
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for (i = 0; i < 64; i += 8)
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{
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long g0 = (long)GET_H_GR (i);
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long g1 = (long)GET_H_GR (i+1);
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long g2 = (long)GET_H_GR (i+2);
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long g3 = (long)GET_H_GR (i+3);
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long g4 = (long)GET_H_GR (i+4);
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long g5 = (long)GET_H_GR (i+5);
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long g6 = (long)GET_H_GR (i+6);
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long g7 = (long)GET_H_GR (i+7);
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if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0)
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sim_io_printf (sd,
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"\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
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i, i+7, g0, g1, g2, g3, g4, g5, g6, g7);
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}
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for (i = 0; i < 64; i += 8)
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{
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long f0 = (long)GET_H_FR (i);
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long f1 = (long)GET_H_FR (i+1);
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long f2 = (long)GET_H_FR (i+2);
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long f3 = (long)GET_H_FR (i+3);
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long f4 = (long)GET_H_FR (i+4);
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long f5 = (long)GET_H_FR (i+5);
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long f6 = (long)GET_H_FR (i+6);
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long f7 = (long)GET_H_FR (i+7);
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if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0)
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sim_io_printf (sd,
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"\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
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i, i+7, f0, f1, f2, f3, f4, f5, f6, f7);
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}
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sim_io_printf (sd,
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"\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
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(long)GET_H_SPR (272),
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(long)GET_H_SPR (273),
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(long)GET_H_SPR (256),
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(long)GET_H_SPR (263));
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}
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break;
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#endif
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}
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}
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/* Handle the MTRAP insn. */
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void
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frv_mtrap (SIM_CPU *current_cpu)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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/* Check the status of media exceptions in MSR0. */
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SI msr = GET_MSR (0);
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if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
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frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
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}
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/* Handle the BREAK insn. */
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void
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frv_break (SIM_CPU *current_cpu)
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{
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IADDR pc;
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SIM_DESC sd = CPU_STATE (current_cpu);
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if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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{
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/* Invalidate the insn cache because the debugger will presumably
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replace the breakpoint insn with the real one. */
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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}
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frv_queue_break_interrupt (current_cpu);
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}
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/* Return from trap. */
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USI
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frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field)
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{
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USI new_pc;
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/* if (normal running mode and debug_field==0
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PC=PCSR
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PSR.ET=1
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PSR.S=PSR.PS
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else if (debug running mode and debug_field==1)
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PC=(BPCSR)
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PSR.ET=BPSR.BET
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PSR.S=BPSR.BS
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change to normal running mode
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*/
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int psr_s = GET_H_PSR_S ();
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int psr_et = GET_H_PSR_ET ();
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/* Check for exceptions in the priority order listed in the FRV Architecture
|
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Volume 2. */
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if (! psr_s)
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{
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/* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
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if (! psr_et)
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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}
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/* privileged_instruction interrupt will have already been queued by
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frv_detect_insn_access_interrupts. */
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new_pc = pc + 4;
|
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}
|
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else if (psr_et)
|
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{
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/* Halt if PSR.S is set. See chapter 6 of the LSI. */
|
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if (psr_s)
|
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{
|
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SIM_DESC sd = CPU_STATE (current_cpu);
|
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
|
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}
|
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|
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frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
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new_pc = pc + 4;
|
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}
|
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else if (! CPU_DEBUG_STATE (current_cpu) && debug_field == 0)
|
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{
|
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USI psr = GET_PSR ();
|
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/* Return from normal running state. */
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new_pc = GET_H_SPR (H_SPR_PCSR);
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SET_PSR_ET (psr, 1);
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SET_PSR_S (psr, GET_PSR_PS (psr));
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sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr);
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}
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else if (CPU_DEBUG_STATE (current_cpu) && debug_field == 1)
|
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{
|
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USI psr = GET_PSR ();
|
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/* Return from debug state. */
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new_pc = GET_H_SPR (H_SPR_BPCSR);
|
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SET_PSR_ET (psr, GET_H_BPSR_BET ());
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SET_PSR_S (psr, GET_H_BPSR_BS ());
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sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr);
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CPU_DEBUG_STATE (current_cpu) = 0;
|
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}
|
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else
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new_pc = pc + 4;
|
||
|
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return new_pc;
|
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}
|
||
|
||
/* Functions for handling non-excepting instruction side effects. */
|
||
static SI next_available_nesr (SIM_CPU *current_cpu, SI current_index)
|
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{
|
||
FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
|
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if (control->spr[H_SPR_NECR].implemented)
|
||
{
|
||
int limit;
|
||
USI necr = GET_NECR ();
|
||
|
||
/* See if any NESRs are implemented. First need to check the validity of
|
||
the NECR. */
|
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if (! GET_NECR_VALID (necr))
|
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return NO_NESR;
|
||
|
||
limit = GET_NECR_NEN (necr);
|
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for (++current_index; current_index < limit; ++current_index)
|
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{
|
||
SI nesr = GET_NESR (current_index);
|
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if (! GET_NESR_VALID (nesr))
|
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return current_index;
|
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}
|
||
}
|
||
return NO_NESR;
|
||
}
|
||
|
||
static SI next_valid_nesr (SIM_CPU *current_cpu, SI current_index)
|
||
{
|
||
FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
|
||
if (control->spr[H_SPR_NECR].implemented)
|
||
{
|
||
int limit;
|
||
USI necr = GET_NECR ();
|
||
|
||
/* See if any NESRs are implemented. First need to check the validity of
|
||
the NECR. */
|
||
if (! GET_NECR_VALID (necr))
|
||
return NO_NESR;
|
||
|
||
limit = GET_NECR_NEN (necr);
|
||
for (++current_index; current_index < limit; ++current_index)
|
||
{
|
||
SI nesr = GET_NESR (current_index);
|
||
if (GET_NESR_VALID (nesr))
|
||
return current_index;
|
||
}
|
||
}
|
||
return NO_NESR;
|
||
}
|
||
|
||
BI
|
||
frvbf_check_non_excepting_load (
|
||
SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index,
|
||
SI immediate_disp, QI data_size, BI is_float
|
||
)
|
||
{
|
||
BI rc = 1; /* perform the load. */
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
int daec = 0;
|
||
int rec = 0;
|
||
int ec = 0;
|
||
USI necr;
|
||
int do_elos;
|
||
SI NE_flags[2];
|
||
SI NE_base;
|
||
SI nesr;
|
||
SI ne_index;
|
||
FRV_REGISTER_CONTROL *control;
|
||
|
||
SI address = GET_H_GR (base_index);
|
||
if (disp_index >= 0)
|
||
address += GET_H_GR (disp_index);
|
||
else
|
||
address += immediate_disp;
|
||
|
||
/* Check for interrupt factors. */
|
||
switch (data_size)
|
||
{
|
||
case NESR_UQI_SIZE:
|
||
case NESR_QI_SIZE:
|
||
break;
|
||
case NESR_UHI_SIZE:
|
||
case NESR_HI_SIZE:
|
||
if (address & 1)
|
||
ec = 1;
|
||
break;
|
||
case NESR_SI_SIZE:
|
||
if (address & 3)
|
||
ec = 1;
|
||
break;
|
||
case NESR_DI_SIZE:
|
||
if (address & 7)
|
||
ec = 1;
|
||
if (target_index & 1)
|
||
rec = 1;
|
||
break;
|
||
case NESR_XI_SIZE:
|
||
if (address & 0xf)
|
||
ec = 1;
|
||
if (target_index & 3)
|
||
rec = 1;
|
||
break;
|
||
default:
|
||
{
|
||
IADDR pc = GET_H_PC ();
|
||
sim_engine_abort (sd, current_cpu, pc,
|
||
"check_non_excepting_load: Incorrect data_size\n");
|
||
break;
|
||
}
|
||
}
|
||
|
||
control = CPU_REGISTER_CONTROL (current_cpu);
|
||
if (control->spr[H_SPR_NECR].implemented)
|
||
{
|
||
necr = GET_NECR ();
|
||
do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr);
|
||
}
|
||
else
|
||
do_elos = 0;
|
||
|
||
/* NECR, NESR, NEEAR are only implemented for the full frv machine. */
|
||
if (do_elos)
|
||
{
|
||
ne_index = next_available_nesr (current_cpu, NO_NESR);
|
||
if (ne_index == NO_NESR)
|
||
{
|
||
IADDR pc = GET_H_PC ();
|
||
sim_engine_abort (sd, current_cpu, pc,
|
||
"No available NESR register\n");
|
||
}
|
||
|
||
/* Fill in the basic fields of the NESR. */
|
||
nesr = GET_NESR (ne_index);
|
||
SET_NESR_VALID (nesr);
|
||
SET_NESR_EAV (nesr);
|
||
SET_NESR_DRN (nesr, target_index);
|
||
SET_NESR_SIZE (nesr, data_size);
|
||
SET_NESR_NEAN (nesr, ne_index);
|
||
if (is_float)
|
||
SET_NESR_FR (nesr);
|
||
else
|
||
CLEAR_NESR_FR (nesr);
|
||
|
||
/* Set the corresponding NEEAR. */
|
||
SET_NEEAR (ne_index, address);
|
||
|
||
SET_NESR_DAEC (nesr, 0);
|
||
SET_NESR_REC (nesr, 0);
|
||
SET_NESR_EC (nesr, 0);
|
||
}
|
||
|
||
/* Set the NE flag corresponding to the target register if an interrupt
|
||
factor was detected.
|
||
daec is not checked here yet, but is declared for future reference. */
|
||
if (is_float)
|
||
NE_base = H_SPR_FNER0;
|
||
else
|
||
NE_base = H_SPR_GNER0;
|
||
|
||
GET_NE_FLAGS (NE_flags, NE_base);
|
||
if (rec)
|
||
{
|
||
SET_NE_FLAG (NE_flags, target_index);
|
||
if (do_elos)
|
||
SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED);
|
||
}
|
||
|
||
if (ec)
|
||
{
|
||
SET_NE_FLAG (NE_flags, target_index);
|
||
if (do_elos)
|
||
SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED);
|
||
}
|
||
|
||
if (do_elos)
|
||
SET_NESR (ne_index, nesr);
|
||
|
||
/* If no interrupt factor was detected then set the NE flag on the
|
||
target register if the NE flag on one of the input registers
|
||
is already set. */
|
||
if (! rec && ! ec && ! daec)
|
||
{
|
||
BI ne_flag = GET_NE_FLAG (NE_flags, base_index);
|
||
if (disp_index >= 0)
|
||
ne_flag |= GET_NE_FLAG (NE_flags, disp_index);
|
||
if (ne_flag)
|
||
{
|
||
SET_NE_FLAG (NE_flags, target_index);
|
||
rc = 0; /* Do not perform the load. */
|
||
}
|
||
else
|
||
CLEAR_NE_FLAG (NE_flags, target_index);
|
||
}
|
||
|
||
SET_NE_FLAGS (NE_base, NE_flags);
|
||
|
||
return rc; /* perform the load? */
|
||
}
|
||
|
||
/* Record state for media exception: media_cr_not_aligned. */
|
||
void
|
||
frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
|
||
{
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
|
||
/* On some machines this generates an illegal_instruction interrupt. */
|
||
switch (STATE_ARCHITECTURE (sd)->mach)
|
||
{
|
||
/* Note: there is a discrepancy between V2.2 of the FR400
|
||
instruction manual and the various FR4xx LSI specs. The former
|
||
claims that unaligned registers cause an mp_exception while the
|
||
latter say it's an illegal_instruction. The LSI specs appear
|
||
to be correct since MTT is fixed at 1. */
|
||
case bfd_mach_fr400:
|
||
case bfd_mach_fr450:
|
||
case bfd_mach_fr550:
|
||
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
|
||
break;
|
||
default:
|
||
frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* Record state for media exception: media_acc_not_aligned. */
|
||
void
|
||
frvbf_media_acc_not_aligned (SIM_CPU *current_cpu)
|
||
{
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
|
||
/* On some machines this generates an illegal_instruction interrupt. */
|
||
switch (STATE_ARCHITECTURE (sd)->mach)
|
||
{
|
||
/* See comment in frvbf_cr_not_aligned(). */
|
||
case bfd_mach_fr400:
|
||
case bfd_mach_fr450:
|
||
case bfd_mach_fr550:
|
||
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
|
||
break;
|
||
default:
|
||
frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* Record state for media exception: media_register_not_aligned. */
|
||
void
|
||
frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
|
||
{
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
|
||
/* On some machines this generates an illegal_instruction interrupt. */
|
||
switch (STATE_ARCHITECTURE (sd)->mach)
|
||
{
|
||
/* See comment in frvbf_cr_not_aligned(). */
|
||
case bfd_mach_fr400:
|
||
case bfd_mach_fr450:
|
||
case bfd_mach_fr550:
|
||
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
|
||
break;
|
||
default:
|
||
frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* Record state for media exception: media_overflow. */
|
||
void
|
||
frvbf_media_overflow (SIM_CPU *current_cpu, int sie)
|
||
{
|
||
frv_set_mp_exception_registers (current_cpu, MTT_OVERFLOW, sie);
|
||
}
|
||
|
||
/* Queue a division exception. */
|
||
enum frv_dtt
|
||
frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt,
|
||
int target_index, int non_excepting)
|
||
{
|
||
/* If there was an overflow and it is masked, then record it in
|
||
ISR.AEXC. */
|
||
USI isr = GET_ISR ();
|
||
if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr))
|
||
{
|
||
dtt &= ~FRV_DTT_OVERFLOW;
|
||
SET_ISR_AEXC (isr);
|
||
SET_ISR (isr);
|
||
}
|
||
if (dtt != FRV_DTT_NO_EXCEPTION)
|
||
{
|
||
if (non_excepting)
|
||
{
|
||
/* Non excepting instruction, simply set the NE flag for the target
|
||
register. */
|
||
SI NE_flags[2];
|
||
GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
|
||
SET_NE_FLAG (NE_flags, target_index);
|
||
SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
|
||
}
|
||
else
|
||
frv_queue_division_exception_interrupt (current_cpu, dtt);
|
||
}
|
||
return dtt;
|
||
}
|
||
|
||
void
|
||
frvbf_check_recovering_store (
|
||
SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float
|
||
)
|
||
{
|
||
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
|
||
int reg_ix;
|
||
|
||
CPU_RSTR_INVALIDATE(current_cpu) = 0;
|
||
|
||
for (reg_ix = next_valid_nesr (current_cpu, NO_NESR);
|
||
reg_ix != NO_NESR;
|
||
reg_ix = next_valid_nesr (current_cpu, reg_ix))
|
||
{
|
||
if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix))
|
||
{
|
||
SI nesr = GET_NESR (reg_ix);
|
||
int nesr_drn = GET_NESR_DRN (nesr);
|
||
BI nesr_fr = GET_NESR_FR (nesr);
|
||
SI remain;
|
||
|
||
/* Invalidate cache block containing this address.
|
||
If we need to count cycles, then the cache operation will be
|
||
initiated from the model profiling functions.
|
||
See frvbf_model_.... */
|
||
if (model_insn)
|
||
{
|
||
CPU_RSTR_INVALIDATE(current_cpu) = 1;
|
||
CPU_LOAD_ADDRESS (current_cpu) = address;
|
||
}
|
||
else
|
||
frv_cache_invalidate (cache, address, 1/* flush */);
|
||
|
||
/* Copy the stored value to the register indicated by NESR.DRN. */
|
||
for (remain = size; remain > 0; remain -= 4)
|
||
{
|
||
SI value;
|
||
|
||
if (is_float)
|
||
value = GET_H_FR (regno);
|
||
else
|
||
value = GET_H_GR (regno);
|
||
|
||
switch (size)
|
||
{
|
||
case 1:
|
||
value &= 0xff;
|
||
break;
|
||
case 2:
|
||
value &= 0xffff;
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
|
||
if (nesr_fr)
|
||
sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn,
|
||
value);
|
||
else
|
||
sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn,
|
||
value);
|
||
|
||
nesr_drn++;
|
||
regno++;
|
||
}
|
||
break; /* Only consider the first matching register. */
|
||
}
|
||
} /* loop over active neear registers. */
|
||
}
|
||
|
||
SI
|
||
frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno)
|
||
{
|
||
/* Only applicable to fr550 */
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
|
||
return;
|
||
|
||
/* On the fr550, media insns in slots 0 and 2 can only access
|
||
accumulators acc0-acc3. Insns in slots 1 and 3 can only access
|
||
accumulators acc4-acc7 */
|
||
switch (frv_current_fm_slot)
|
||
{
|
||
case UNIT_FM0:
|
||
case UNIT_FM2:
|
||
if (regno <= 3)
|
||
return 1; /* all is ok */
|
||
break;
|
||
case UNIT_FM1:
|
||
case UNIT_FM3:
|
||
if (regno >= 4)
|
||
return 1; /* all is ok */
|
||
break;
|
||
}
|
||
|
||
/* The specified accumulator is out of range. Queue an illegal_instruction
|
||
interrupt. */
|
||
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
|
||
return 0;
|
||
}
|
||
|
||
void
|
||
frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
|
||
{
|
||
/* Only applicable to fr550 */
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
|
||
return;
|
||
|
||
/* Adress must be aligned on a word boundary. */
|
||
if (address & 0x3)
|
||
frv_queue_data_access_exception_interrupt (current_cpu);
|
||
}
|
||
|
||
static void
|
||
clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float)
|
||
{
|
||
int reg_ix;
|
||
|
||
/* Only implemented for full frv. */
|
||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_frv)
|
||
return;
|
||
|
||
/* Clear the appropriate NESR and NEEAR registers. */
|
||
for (reg_ix = next_valid_nesr (current_cpu, NO_NESR);
|
||
reg_ix != NO_NESR;
|
||
reg_ix = next_valid_nesr (current_cpu, reg_ix))
|
||
{
|
||
SI nesr;
|
||
/* The register is available, now check if it is active. */
|
||
nesr = GET_NESR (reg_ix);
|
||
if (GET_NESR_FR (nesr) == is_float)
|
||
{
|
||
if (target_index < 0 || GET_NESR_DRN (nesr) == target_index)
|
||
{
|
||
SET_NESR (reg_ix, 0);
|
||
SET_NEEAR (reg_ix, 0);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
static void
|
||
clear_ne_flags (
|
||
SIM_CPU *current_cpu,
|
||
SI target_index,
|
||
int hi_available,
|
||
int lo_available,
|
||
SI NE_base
|
||
)
|
||
{
|
||
SI NE_flags[2];
|
||
int exception;
|
||
|
||
GET_NE_FLAGS (NE_flags, NE_base);
|
||
if (target_index >= 0)
|
||
CLEAR_NE_FLAG (NE_flags, target_index);
|
||
else
|
||
{
|
||
if (lo_available)
|
||
NE_flags[1] = 0;
|
||
if (hi_available)
|
||
NE_flags[0] = 0;
|
||
}
|
||
SET_NE_FLAGS (NE_base, NE_flags);
|
||
}
|
||
|
||
/* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
|
||
means to check for any register available. */
|
||
static void
|
||
which_registers_available (
|
||
SIM_CPU *current_cpu, int *hi_available, int *lo_available, int is_float
|
||
)
|
||
{
|
||
if (is_float)
|
||
frv_fr_registers_available (current_cpu, hi_available, lo_available);
|
||
else
|
||
frv_gr_registers_available (current_cpu, hi_available, lo_available);
|
||
}
|
||
|
||
void
|
||
frvbf_clear_ne_flags (SIM_CPU *current_cpu, SI target_index, BI is_float)
|
||
{
|
||
int hi_available;
|
||
int lo_available;
|
||
int exception;
|
||
SI NE_base;
|
||
USI necr;
|
||
FRV_REGISTER_CONTROL *control;
|
||
|
||
/* Check for availability of the target register(s). */
|
||
which_registers_available (current_cpu, & hi_available, & lo_available,
|
||
is_float);
|
||
|
||
/* Check to make sure that the target register is available. */
|
||
if (! frv_check_register_access (current_cpu, target_index,
|
||
hi_available, lo_available))
|
||
return;
|
||
|
||
/* Determine whether we're working with GR or FR registers. */
|
||
if (is_float)
|
||
NE_base = H_SPR_FNER0;
|
||
else
|
||
NE_base = H_SPR_GNER0;
|
||
|
||
/* Always clear the appropriate NE flags. */
|
||
clear_ne_flags (current_cpu, target_index, hi_available, lo_available,
|
||
NE_base);
|
||
|
||
/* Clear the appropriate NESR and NEEAR registers. */
|
||
control = CPU_REGISTER_CONTROL (current_cpu);
|
||
if (control->spr[H_SPR_NECR].implemented)
|
||
{
|
||
necr = GET_NECR ();
|
||
if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr))
|
||
clear_nesr_neear (current_cpu, target_index, is_float);
|
||
}
|
||
}
|
||
|
||
void
|
||
frvbf_commit (SIM_CPU *current_cpu, SI target_index, BI is_float)
|
||
{
|
||
SI NE_base;
|
||
SI NE_flags[2];
|
||
BI NE_flag;
|
||
int exception;
|
||
int hi_available;
|
||
int lo_available;
|
||
USI necr;
|
||
FRV_REGISTER_CONTROL *control;
|
||
|
||
/* Check for availability of the target register(s). */
|
||
which_registers_available (current_cpu, & hi_available, & lo_available,
|
||
is_float);
|
||
|
||
/* Check to make sure that the target register is available. */
|
||
if (! frv_check_register_access (current_cpu, target_index,
|
||
hi_available, lo_available))
|
||
return;
|
||
|
||
/* Determine whether we're working with GR or FR registers. */
|
||
if (is_float)
|
||
NE_base = H_SPR_FNER0;
|
||
else
|
||
NE_base = H_SPR_GNER0;
|
||
|
||
/* Determine whether a ne exception is pending. */
|
||
GET_NE_FLAGS (NE_flags, NE_base);
|
||
if (target_index >= 0)
|
||
NE_flag = GET_NE_FLAG (NE_flags, target_index);
|
||
else
|
||
{
|
||
NE_flag =
|
||
hi_available && NE_flags[0] != 0 || lo_available && NE_flags[1] != 0;
|
||
}
|
||
|
||
/* Always clear the appropriate NE flags. */
|
||
clear_ne_flags (current_cpu, target_index, hi_available, lo_available,
|
||
NE_base);
|
||
|
||
control = CPU_REGISTER_CONTROL (current_cpu);
|
||
if (control->spr[H_SPR_NECR].implemented)
|
||
{
|
||
necr = GET_NECR ();
|
||
if (GET_NECR_VALID (necr) && GET_NECR_ELOS (necr) && NE_flag)
|
||
{
|
||
/* Clear the appropriate NESR and NEEAR registers. */
|
||
clear_nesr_neear (current_cpu, target_index, is_float);
|
||
frv_queue_program_interrupt (current_cpu, FRV_COMMIT_EXCEPTION);
|
||
}
|
||
}
|
||
}
|
||
|
||
/* Generate the appropriate fp_exception(s) based on the given status code. */
|
||
void
|
||
frvbf_fpu_error (CGEN_FPU* fpu, int status)
|
||
{
|
||
struct frv_fp_exception_info fp_info = {
|
||
FSR_NO_EXCEPTION, FTT_IEEE_754_EXCEPTION
|
||
};
|
||
|
||
if (status &
|
||
(sim_fpu_status_invalid_snan |
|
||
sim_fpu_status_invalid_qnan |
|
||
sim_fpu_status_invalid_isi |
|
||
sim_fpu_status_invalid_idi |
|
||
sim_fpu_status_invalid_zdz |
|
||
sim_fpu_status_invalid_imz |
|
||
sim_fpu_status_invalid_cvi |
|
||
sim_fpu_status_invalid_cmp |
|
||
sim_fpu_status_invalid_sqrt))
|
||
fp_info.fsr_mask |= FSR_INVALID_OPERATION;
|
||
|
||
if (status & sim_fpu_status_invalid_div0)
|
||
fp_info.fsr_mask |= FSR_DIVISION_BY_ZERO;
|
||
|
||
if (status & sim_fpu_status_inexact)
|
||
fp_info.fsr_mask |= FSR_INEXACT;
|
||
|
||
if (status & sim_fpu_status_overflow)
|
||
fp_info.fsr_mask |= FSR_OVERFLOW;
|
||
|
||
if (status & sim_fpu_status_underflow)
|
||
fp_info.fsr_mask |= FSR_UNDERFLOW;
|
||
|
||
if (status & sim_fpu_status_denorm)
|
||
{
|
||
fp_info.fsr_mask |= FSR_DENORMAL_INPUT;
|
||
fp_info.ftt = FTT_DENORMAL_INPUT;
|
||
}
|
||
|
||
if (fp_info.fsr_mask != FSR_NO_EXCEPTION)
|
||
{
|
||
SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner;
|
||
frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
|
||
}
|
||
}
|