mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-15 04:31:49 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
777 lines
14 KiB
ArmAsm
777 lines
14 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Include Files /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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include(std.inc)
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include(selfcheck.inc)
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include(symtable.inc)
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include(mmrs.inc)
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Defines /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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#ifndef USER_CODE_SPACE
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#define USER_CODE_SPACE CODE_ADDR_1 //
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000010
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#endif
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#ifndef ITABLE
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#define ITABLE CODE_ADDR_2 //
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#endif
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// RESET ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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RST_ISR :
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// Initialize Dregs
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INIT_R_REGS(0);
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// Initialize Pregs
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INIT_P_REGS(0);
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// Initialize ILBM Registers
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INIT_I_REGS(0);
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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// Initialize the Address of the Checkreg data segment
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// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
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CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
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// Setup User Stack
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LD32_LABEL(sp, USTACK);
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USP = SP;
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// Setup Kernel Stack
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LD32_LABEL(sp, KSTACK);
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// Setup Frame Pointer
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FP = SP;
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// Setup Event Vector Table
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LD32(p0, EVT0);
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LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
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[ P0 ++ ] = R0;
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// Setup the EVT_OVERRIDE MMR
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R0 = 0;
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LD32(p0, EVT_OVERRIDE);
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[ P0 ] = R0;
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// Setup Interrupt Mask
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R0 = -1;
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LD32(p0, IMASK);
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[ P0 ] = R0;
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// Return to Supervisor Code
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RAISE 15;
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NOP;
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LD32_LABEL(r0, USER_CODE);
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RETI = R0;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EMU ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EMU_ISR :
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RTE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// NMI ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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NMI_ISR :
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RTN;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EXC ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EXC_ISR :
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RTX;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// HWE ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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HWE_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// TMR ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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TMR_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV7 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV7_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV8 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV8_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV9 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV9_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV10 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV10_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV11 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV11_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV12 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV12_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV13 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV13_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV14 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV14_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV15 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV15_ISR :
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P0 = 0x5 (Z);
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P1 = 0xa (Z);
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NOP;
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NOP;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// USER CODE /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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USER_CODE :
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/////////////////////////////////////////////////////////////////////////////
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// Loop 0 (Kill Lsetup in WB)
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/////////////////////////////////////////////////////////////////////////////
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EXCPT 0x5;
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LSETUP ( L0T , L0T ) LC0 = P0;
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L0T:R0 += 5;
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EXCPT 0x5;
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LSETUP ( L1T , L1B ) LC0 = P0;
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L1T:R0 += 5;
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L1B:R1 += 4;
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EXCPT 0x5;
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LSETUP ( L2T , L2B ) LC0 = P0;
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L2T:R0 += 5;
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R1 += 4;
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L2B:R2 += 3;
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EXCPT 0x5;
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LSETUP ( L3T , L3B ) LC0 = P0;
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L3T:R0 += 5;
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R1 += 4;
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R2 += 3;
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L3B:R3 += 2;
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EXCPT 0x5;
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LSETUP ( L4T , L4B ) LC0 = P0;
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L4T:R0 += 5;
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R1 += 4;
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R2 += 3;
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R3 += 2;
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L4B:R4 += 1;
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/////////////////////////////////////////////////////////////////////////////
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// Loop 1 (Kill Lsetup in WB)
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/////////////////////////////////////////////////////////////////////////////
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EXCPT 0x5;
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LSETUP ( M0T , M0T ) LC1 = P0;
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M0T:R0 += 5;
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EXCPT 0x5;
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LSETUP ( M1T , M1B ) LC1 = P0;
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M1T:R0 += 5;
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M1B:R1 += 4;
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EXCPT 0x5;
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LSETUP ( M2T , M2B ) LC1 = P0;
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M2T:R0 += 5;
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R1 += 4;
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M2B:R2 += 3;
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EXCPT 0x5;
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LSETUP ( M3T , M3B ) LC1 = P0;
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M3T:R0 += 5;
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R1 += 4;
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R2 += 3;
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M3B:R3 += 2;
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EXCPT 0x5;
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LSETUP ( M4T , M4B ) LC1 = P0;
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M4T:R0 += 5;
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R1 += 4;
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R2 += 3;
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R3 += 2;
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M4B:R4 += 1;
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/////////////////////////////////////////////////////////////////////////////
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// Loop 0 (Kill during the last iteration at each pipe stage)
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/////////////////////////////////////////////////////////////////////////////
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LSETUP ( N0T , N0B ) LC0 = P1;
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NOP;
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N0T:R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP N0B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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N0B:R2 += 3;
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LSETUP ( N1T , N1B ) LC0 = P1;
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NOP;
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N1T:R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP N1B (BP);
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EXCPT 0x5;
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N1B:R2 += 3;
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LSETUP ( N2T , N2B ) LC0 = P1;
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NOP;
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N2T:R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP N2B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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N2B:R2 += 3;
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LSETUP ( N3T , N3B ) LC0 = P1;
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NOP;
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N3T:R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP N3B (BP);
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EXCPT 0x5;
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R3 += 4;
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N3B:R2 += 3;
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LSETUP ( N4T , N4B ) LC0 = P1;
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NOP;
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N4T:R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP N4B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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N4B:R2 += 3;
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LSETUP ( N5T , N5B ) LC0 = P1;
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NOP;
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N5T:R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP N5B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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N5B:R2 += 3;
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LSETUP ( N6T , N6B ) LC0 = P1;
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NOP;
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N6T:R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP N6B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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N6B:R2 += 3;
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LSETUP ( N7T , N7B ) LC0 = P1;
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NOP;
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N7T:R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP N7B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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N7B:R2 += 3;
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LSETUP ( N8T , N8B ) LC0 = P1;
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NOP;
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N8T:R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP N8B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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N8B:R2 += 3;
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LSETUP ( N9T , N9B ) LC0 = P1;
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NOP;
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N9T:R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP N9B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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N9B:R2 += 3;
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LSETUP ( NAT , NAB ) LC0 = P1;
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NOP;
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NAT:
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R0 = LC0;
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CC = R0 == 1;
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IF !CC JUMP NAB (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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R7 += 8;
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NAB:
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R2 += 3;
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LSETUP ( NBT , NBB ) LC0 = P1;
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NOP;
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NBT:
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R0 = LC0;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP NBB (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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R7 += 8;
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NBB:
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R2 += 3;
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/////////////////////////////////////////////////////////////////////////////
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// Loop 1 (Kill during the last iteration at each pipe stage)
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/////////////////////////////////////////////////////////////////////////////
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LSETUP ( O0T , O0B ) LC1 = P1;
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NOP;
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O0T:R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP O0B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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O0B:R2 += 3;
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LSETUP ( O1T , O1B ) LC1 = P1;
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NOP;
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O1T:R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP O1B (BP);
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EXCPT 0x5;
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O1B:R2 += 3;
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LSETUP ( O2T , O2B ) LC1 = P1;
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NOP;
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O2T:R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP O2B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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O2B:R2 += 3;
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LSETUP ( O3T , O3B ) LC1 = P1;
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NOP;
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O3T:R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP O3B (BP);
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EXCPT 0x5;
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R3 += 4;
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O3B:R2 += 3;
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LSETUP ( O4T , O4B ) LC1 = P1;
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NOP;
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O4T:R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP O4B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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O4B:R2 += 3;
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LSETUP ( O5T , O5B ) LC1 = P1;
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NOP;
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O5T:R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP O5B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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O5B:R2 += 3;
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LSETUP ( O6T , O6B ) LC1 = P1;
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NOP;
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O6T:R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP O6B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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O6B:R2 += 3;
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LSETUP ( O7T , O7B ) LC1 = P1;
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NOP;
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O7T:R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP O7B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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O7B:R2 += 3;
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LSETUP ( O8T , O8B ) LC1 = P1;
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NOP;
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O8T:R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP O8B (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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O8B:R2 += 3;
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LSETUP ( O9T , O9B ) LC1 = P1;
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NOP;
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O9T:R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP O9B (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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O9B:R2 += 3;
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LSETUP ( OAT , OAB ) LC1 = P1;
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NOP;
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OAT:
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R0 = LC1;
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CC = R0 == 1;
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IF !CC JUMP OAB (BP);
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R0 += 1;
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R1 += 2;
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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R7 += 8;
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OAB:
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R2 += 3;
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LSETUP ( OBT , OBB ) LC1 = P1;
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NOP;
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OBT:
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R0 = LC1;
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R0 += 1;
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R1 += 2;
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CC = R0 == 1;
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IF !CC JUMP OBB (BP);
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EXCPT 0x5;
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R3 += 4;
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R4 += 5;
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R5 += 6;
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R6 += 7;
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R7 += 8;
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OBB:
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R2 += 3;
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NOP;
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NOP;
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NOP;
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dbg_pass; // Call Endtest Macro
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// DATA MEMRORY /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
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.dd 0xdeadbeef;
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.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
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|
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
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.dd 0x02020202;
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|
.dd 0x03030303;
|
|
.dd 0x04040404;
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|
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// Define Kernal Stack
|
|
.data
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.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
|
|
KSTACK :
|
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|
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.space (STACKSIZE);
|
|
USTACK :
|
|
|
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/////////////////////////////////////////////////////////////////////////////
|
|
///////////////////////// END OF TEST /////////////////////////////
|
|
/////////////////////////////////////////////////////////////////////////////
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