mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
520 lines
11 KiB
ArmAsm
520 lines
11 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Include Files /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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include(std.inc)
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include(selfcheck.inc)
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include(symtable.inc)
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include(mmrs.inc)
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Defines /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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#ifndef USER_CODE_SPACE
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#define USER_CODE_SPACE CODE_ADDR_1 //
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000010
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#endif
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#ifndef ITABLE
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#define ITABLE CODE_ADDR_2 //
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#endif
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// RESET ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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RST_ISR :
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// Initialize Dregs
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INIT_R_REGS(0);
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// Initialize Pregs
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INIT_P_REGS(0);
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// Initialize ILBM Registers
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INIT_I_REGS(0);
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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// Initialize the Address of the Checkreg data segment
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// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
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CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
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// Setup User Stack
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LD32_LABEL(sp, USTACK);
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USP = SP;
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// Setup Kernel Stack
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LD32_LABEL(sp, KSTACK);
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// Setup Frame Pointer
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FP = SP;
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// Setup Event Vector Table
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LD32(p0, EVT0);
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LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
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[ P0 ++ ] = R0;
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// Setup the EVT_OVERRIDE MMR
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R0 = 0;
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LD32(p0, EVT_OVERRIDE);
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[ P0 ] = R0;
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// Setup Interrupt Mask
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R0 = -1;
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LD32(p0, IMASK);
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[ P0 ] = R0;
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// Return to Supervisor Code
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RAISE 15;
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NOP;
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LD32_LABEL(r0, USER_CODE);
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RETI = R0;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EMU ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EMU_ISR :
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RTE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// NMI ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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NMI_ISR :
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RTN;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EXC ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EXC_ISR :
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RTX;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// HWE ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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HWE_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// TMR ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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TMR_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV7 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV7_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV8 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV8_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV9 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV9_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV10 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV10_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV11 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV11_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV12 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV12_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV13 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV13_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV14 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV14_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV15 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV15_ISR :
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P0 = 0x5 (Z);
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LSETUP ( l0s , l0s ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l0s:[ -- SP ] = ( R7:5 );
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LSETUP ( l1s , l1e ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l1s:R5 += 1;
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l1e:[ -- SP ] = ( R7:5 );
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LSETUP ( l2s , l2e ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l2s:R5 += 1;
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R6 += 2;
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l2e:[ -- SP ] = ( R7:5 );
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LSETUP ( l3s , l3e ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l3s:R5 += 1;
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R6 += 2;
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R7 += 3;
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l3e:[ -- SP ] = ( R7:5 );
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LSETUP ( l4s , l4e ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l4s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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l4e:[ -- SP ] = ( R7:4 );
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LSETUP ( l5s , l5e ) LC0 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l5s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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R5 += 3;
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l5e:[ -- SP ] = ( R7:4 );
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LSETUP ( l6s , l6e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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l6s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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R5 += 3;
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R7 += 5;
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l6e:[ -- SP ] = ( R7:4 );
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NOP;
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LSETUP ( m0s , m0s ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m0s:[ -- SP ] = ( R7:5 );
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LSETUP ( m1s , m1e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m1s:R5 += 1;
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m1e:[ -- SP ] = ( R7:5 );
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LSETUP ( m2s , m2e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m2s:R5 += 1;
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R6 += 2;
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m2e:[ -- SP ] = ( R7:5 );
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LSETUP ( m3s , m3e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m3s:R5 += 1;
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R6 += 2;
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R7 += 3;
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m3e:[ -- SP ] = ( R7:5 );
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LSETUP ( m4s , m4e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m4s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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m4e:[ -- SP ] = ( R7:4 );
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LSETUP ( m5s , m5e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m5s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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R5 += 3;
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m5e:[ -- SP ] = ( R7:4 );
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LSETUP ( m6s , m6e ) LC1 = P0;
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R0 += 1;
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R4 += 3;
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R5 += 5;
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m6s:R5 += 1;
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R6 += 2;
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R7 += 3;
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R4 += 4;
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R5 += 3;
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R7 += 5;
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m6e:[ -- SP ] = ( R7:4 );
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NOP;
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NOP;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// USER CODE /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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USER_CODE :
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NOP;
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NOP;
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NOP;
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NOP;
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dbg_pass; // Call Endtest Macro
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// DATA MEMRORY /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
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.dd 0xdeadbeef;
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.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
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.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
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.dd 0x02020202;
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.dd 0x03030303;
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.dd 0x04040404;
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// Define Kernal Stack
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.data
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.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
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KSTACK :
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.space (STACKSIZE);
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USTACK :
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// END OF TEST /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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