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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
308 lines
9.2 KiB
ArmAsm
308 lines
9.2 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp
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// Description: Default protection checks (CPLB disabled)
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// - MMR access in User mode
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// - DAG1 Access MMRs (supv/user mode, read/write)
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// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write)
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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#define EXCPT_PROTVIOL 0x23
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#define OMODE_SUPV 0 // not used in the hardware
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CHECK_INIT(p5, 0xE0000000);
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// setup interrupt controller with exception handler address
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WR_MMR_LABEL(EVT3, handler, p0, r1);
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WR_MMR_LABEL(EVT15, Supv, p0, r1);
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WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
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WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
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CSYNC;
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A0 = 0;
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// go to user mode. and enable exceptions
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LD32_LABEL(r0, User);
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RETI = R0;
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// But first raise interrupt 15 so we can run in supervisor mode.
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RAISE 15;
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RTI;
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Supv:
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//-------------------------------------------------------
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// DAG1 MMR Write access
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LD32(i1, (DCPLB_ADDR0));
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LD32_LABEL(p2, Y01); // Exception handler will return to this address
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LD32(r0, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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Y01:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG1 MMR Read access
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LD32(i1, (DCPLB_ADDR1));
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LD32_LABEL(p2, Y02); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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Y02:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!)
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#if 0
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//-------------------------------------------------------
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// DAG1 Scratch SRAM Write access
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LD32(i1, (( 0xFF800000 + 0x300000)));
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LD32_LABEL(p2, Y03); // Exception handler will return to this address
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LD32(r1, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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Y03:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG1 Scratch SRAM Read access
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LD32(i1, ((( 0xFF800000 + 0x300000) + 4)));
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LD32_LABEL(p2, Y04); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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Y04:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!)
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#endif
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//-------------------------------------------------------
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// Now, go to User mode
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LD32_LABEL(r0, User);
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RETI = R0;
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RTI;
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User:
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//-------------------------------------------------------
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// DAG0 MMR Write access (multi-issue)
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LD32(i1, (DCPLB_ADDR0));
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LD32_LABEL(p2, Y11); // Exception handler will return to this address
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LD32(r0, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here
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Y11:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG0 MMR Read access (multi-issue)
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LD32(i1, (DCPLB_ADDR1));
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LD32_LABEL(p2, Y12); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here
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Y12:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG1 MMR Write access
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LD32(i1, (DCPLB_ADDR0));
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LD32_LABEL(p2, Y13); // Exception handler will return to this address
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LD32(r0, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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Y13:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG1 MMR Read access
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LD32(i1, (DCPLB_ADDR1));
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LD32_LABEL(p2, Y14); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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Y14:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!)
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#if 0
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//-------------------------------------------------------
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// DAG1 Scratch SRAM Write access
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LD32(i1, (( 0xFF800000 + 0x300000)));
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LD32_LABEL(p2, Y15); // Exception handler will return to this address
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LD32(r1, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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Y15:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG1 Scratch SRAM Read access
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LD32(i1, ((( 0xFF800000 + 0x300000) + 4)));
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LD32_LABEL(p2, Y16); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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Y16:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!)
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#endif
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//-------------------------------------------------------
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// DAG0 MMR Write access (single-issue)
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LD32(i1, (DCPLB_ADDR0));
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LD32_LABEL(p2, Y17); // Exception handler will return to this address
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LD32(r0, 0xdeadbeef);
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X17: [ I1 ] = R1; // Exception should occur here
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Y17:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// DAG0 MMR Read access (single-issue)
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LD32(i1, (DCPLB_ADDR1));
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LD32_LABEL(p2, Y18); // Exception handler will return to this address
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R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X18: R1 = [ I1 ]; // Exception should occur here
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Y18:
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// Now check that handler read correct values
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CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT
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CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS
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CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS
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CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!)
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//-------------------------------------------------------
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dbg_pass;
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handler:
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R4 = SEQSTAT; // Get exception cause
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// read and check fail addr (addr_which_causes_exception)
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// should not be set for alignment exception
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RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
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RD_MMR(DCPLB_STATUS, p0, r6);
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R7 = RETX; // get address of excepting instruction
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RETX = P2;
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RTX;
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