mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
545 lines
12 KiB
ArmAsm
545 lines
12 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/debug/dbg_brtkn_nprd_src_kill/dbg_brtkn_nprd_src_kill.dsp
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// Description: This test checks that the trace buffer keeps track of a
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// branch source instruction that is taken but not predicted getting killed
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// at each stage in the pipe. The test consists of 8 instances of an EXCPT
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// instruction followed by 0 to 7 NOPs and a BRT instruction (no bp), with
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// the trace buffer enabled.
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Include Files /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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include(std.inc)
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include(selfcheck.inc)
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include(symtable.inc)
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include(mmrs.inc)
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Defines /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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#ifndef USER_CODE_SPACE
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#define USER_CODE_SPACE CODE_ADDR_1 //
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000020
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#endif
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#ifndef ITABLE
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#define ITABLE CODE_ADDR_2 //
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#endif
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// RESET ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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RST_ISR :
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// Initialize Dregs
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INIT_R_REGS(0);
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// Initialize Pregs
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INIT_P_REGS(0);
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// Initialize ILBM Registers
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INIT_I_REGS(0);
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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// Initialize the Address of the Checkreg data segment
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// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
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CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
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// Setup User Stack
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LD32_LABEL(sp, USTACK);
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USP = SP;
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// Setup Kernel Stack
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LD32_LABEL(sp, KSTACK);
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// Setup Frame Pointer
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FP = SP;
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// Setup Event Vector Table
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LD32(p0, EVT0);
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LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
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[ P0 ++ ] = R0;
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// Setup the EVT_OVERRIDE MMR
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R0 = 0;
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LD32(p0, EVT_OVERRIDE);
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[ P0 ] = R0;
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// Setup Interrupt Mask
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R0 = -1;
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LD32(p0, IMASK);
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[ P0 ] = R0;
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// Return to Supervisor Code
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RAISE 15;
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NOP;
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LD32_LABEL(r0, USER_CODE);
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RETI = R0;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EMU ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EMU_ISR :
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RTE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// NMI ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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NMI_ISR :
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RTN;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EXC ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EXC_ISR :
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// Save all the registers used in the ISR
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[ -- SP ] = R0;
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[ -- SP ] = R1;
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[ -- SP ] = P0;
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[ -- SP ] = P1;
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[ -- SP ] = LC0;
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[ -- SP ] = LB0;
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[ -- SP ] = LT0;
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[ -- SP ] = ASTAT;
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// Get EXCAUSE bits out of SEQSTAT
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R0 = SEQSTAT;
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R0 = R0 << 26;
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R0 = R0 >> 26;
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// Check for Trace Exception
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// Load r1 with EXCAUSE for Trace Exception
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R1 = 0x0011 (Z);
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// Check for Trace Exception
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CC = R0 == R1;
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// Branch to OUT if the EXCAUSE is not TRACE.
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IF !CC JUMP OUT;
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// Read out the Trace Buffer.
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LD32(p0, TBUFSTAT);
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// Read TBUFSTAT MMR
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P1 = [ P0 ];
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// if p1 is zero skip the loop.
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CC = P1 == 0;
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IF CC JUMP OUT;
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// Read out the Entire Trace Buffer.
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LD32(p0, TBUF);
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LSETUP ( l0s , l0e ) LC0 = P1;
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l0s:R0 = [ P0 ];
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l0e:R0 = [ P0 ];
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OUT:
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// Check for other exception, if any.
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// Restore all saved registers.
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ASTAT = [ SP ++ ];
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LT0 = [ SP ++ ];
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LB0 = [ SP ++ ];
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LC0 = [ SP ++ ];
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P1 = [ SP ++ ];
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P0 = [ SP ++ ];
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R1 = [ SP ++ ];
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R0 = [ SP ++ ];
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// Return
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RTX;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// HWE ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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HWE_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// TMR ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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TMR_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV7 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV7_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV8 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV8_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV9 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV9_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV10 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV10_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV11 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV11_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV12 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV12_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV13 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV13_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV14 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV14_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV15 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV15_ISR :
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WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow
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CSYNC; // Wait for MMR write to complete
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CC = R7 == R6; // Set CC
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EXCPT 1;
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IF CC JUMP 4; // Mispredicted branch gets killed in WB stage
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NOP;
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NOP;
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EXCPT 2;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in EX3 stage
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NOP;
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NOP;
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EXCPT 3;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in EX2 stage
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NOP;
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NOP;
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EXCPT 4;
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NOP;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in EX1 stage
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NOP;
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NOP;
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EXCPT 5;
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NOP;
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NOP;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in AC stage
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NOP;
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NOP;
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EXCPT 6;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in DEC stage
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NOP;
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NOP;
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EXCPT 7; NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in IF2 stage
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NOP;
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NOP;
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EXCPT 8;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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IF CC JUMP 4; // Mispredicted branch gets killed in IF1 stage
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NOP;
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NOP;
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// Read out the Rest of the Trace Buffer.
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LD32(p0, TBUFSTAT);
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// Read TBUFSTAT MMR
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P1 = [ P0 ];
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// if p1 is zero skip the loop.
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CC = P1 == 0;
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IF CC JUMP OUT1;
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// Read out the Entire Trace Buffer.
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LD32(p0, TBUF);
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LSETUP ( l1s , l1e ) LC0 = P1;
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l1s:R0 = [ P0 ];
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l1e:R0 = [ P0 ];
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// Don't RTI if you never wish to go to User Mode
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// use END_TEST instead.
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OUT1:
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dbg_pass;
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// rti;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// USER CODE /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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USER_CODE :
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// YOUR USER CODE GOES HERE.
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dbg_pass; // Call Endtest Macro
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// DATA MEMRORY /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
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.dd 0x01010101;
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.dd 0x02020202;
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.dd 0x03030303;
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.dd 0x04040404;
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.dd 0x05050505;
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.dd 0x06060606;
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.dd 0x07070707;
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.dd 0x08080808;
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.dd 0x09090909;
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.dd 0x0a0a0a0a;
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.dd 0x0b0b0b0b;
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.dd 0x0c0c0c0c;
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.dd 0x0d0d0d0d;
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.dd 0x0e0e0e0e;
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.dd 0x0f0f0f0f;
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// Define Kernal Stack
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.section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw"
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.space (STACKSIZE);
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KSTACK :
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.space (STACKSIZE);
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USTACK :
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// END OF TEST /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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