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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
383 lines
5.4 KiB
ArmAsm
383 lines
5.4 KiB
ArmAsm
//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp
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// Spec Reference: regmv preg-to-imlb reg
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# mach: bfin
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.include "testutils.inc"
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start
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// check R-reg to imlb-reg move
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imm32 r0, 0x00000001;
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imm32 p1, 0x00020003;
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imm32 p2, 0x00040005;
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imm32 p3, 0x00060007;
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imm32 p4, 0x00080009;
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imm32 p5, 0x000a000b;
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imm32 sp, 0x000c000d;
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imm32 fp, 0x000e000f;
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I0 = P1;
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I1 = P1;
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I2 = P1;
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I3 = P1;
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M0 = P1;
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M1 = P1;
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M2 = P1;
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M3 = P1;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00020003;
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CHECKREG r1, 0x00020003;
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CHECKREG r2, 0x00020003;
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CHECKREG r3, 0x00020003;
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CHECKREG r4, 0x00020003;
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CHECKREG r5, 0x00020003;
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CHECKREG r6, 0x00020003;
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CHECKREG r7, 0x00020003;
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imm32 p2, 0x00040005;
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I0 = P2;
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I1 = P2;
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I2 = P2;
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I3 = P2;
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M0 = P2;
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M1 = P2;
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M2 = P2;
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M3 = P2;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00040005;
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CHECKREG r1, 0x00040005;
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CHECKREG r2, 0x00040005;
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CHECKREG r3, 0x00040005;
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CHECKREG r4, 0x00040005;
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CHECKREG r5, 0x00040005;
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CHECKREG r6, 0x00040005;
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CHECKREG r7, 0x00040005;
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imm32 p3, 0x00060007;
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I0 = P3;
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I1 = P3;
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I2 = P3;
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I3 = P3;
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M0 = P3;
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M1 = P3;
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M2 = P3;
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M3 = P3;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00060007;
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CHECKREG r1, 0x00060007;
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CHECKREG r2, 0x00060007;
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CHECKREG r3, 0x00060007;
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CHECKREG r4, 0x00060007;
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CHECKREG r5, 0x00060007;
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CHECKREG r6, 0x00060007;
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CHECKREG r7, 0x00060007;
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imm32 p4, 0x00080009;
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I0 = P4;
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I1 = P4;
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I2 = P4;
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I3 = P4;
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M0 = P4;
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M1 = P4;
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M2 = P4;
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M3 = P4;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00080009;
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CHECKREG r1, 0x00080009;
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CHECKREG r2, 0x00080009;
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CHECKREG r3, 0x00080009;
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CHECKREG r4, 0x00080009;
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CHECKREG r5, 0x00080009;
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CHECKREG r6, 0x00080009;
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CHECKREG r7, 0x00080009;
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imm32 p5, 0x000a000b;
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I0 = P5;
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I1 = P5;
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I2 = P5;
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I3 = P5;
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M0 = P5;
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M1 = P5;
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M2 = P5;
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M3 = P5;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x000a000b;
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CHECKREG r1, 0x000a000b;
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CHECKREG r2, 0x000a000b;
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CHECKREG r3, 0x000a000b;
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CHECKREG r4, 0x000a000b;
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CHECKREG r5, 0x000a000b;
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CHECKREG r6, 0x000a000b;
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CHECKREG r7, 0x000a000b;
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imm32 sp, 0x000c000d;
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I0 = SP;
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I1 = SP;
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I2 = SP;
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I3 = SP;
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M0 = SP;
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M1 = SP;
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M2 = SP;
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M3 = SP;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x000c000d;
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CHECKREG r1, 0x000c000d;
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CHECKREG r2, 0x000c000d;
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CHECKREG r3, 0x000c000d;
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CHECKREG r4, 0x000c000d;
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CHECKREG r5, 0x000c000d;
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CHECKREG r6, 0x000c000d;
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CHECKREG r7, 0x000c000d;
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imm32 fp, 0x000e000f;
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I0 = FP;
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I1 = FP;
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I2 = FP;
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I3 = FP;
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M0 = FP;
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M1 = FP;
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M2 = FP;
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M3 = FP;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x000e000f;
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CHECKREG r1, 0x000e000f;
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CHECKREG r2, 0x000e000f;
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CHECKREG r3, 0x000e000f;
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CHECKREG r4, 0x000e000f;
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CHECKREG r5, 0x000e000f;
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CHECKREG r6, 0x000e000f;
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CHECKREG r7, 0x000e000f;
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imm32 p1, 0x00020003;
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L0 = P1;
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L1 = P1;
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L2 = P1;
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L3 = P1;
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B0 = P1;
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B1 = P1;
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B2 = P1;
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B3 = P1;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00020003;
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CHECKREG r1, 0x00020003;
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CHECKREG r2, 0x00020003;
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CHECKREG r3, 0x00020003;
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CHECKREG r4, 0x00020003;
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CHECKREG r5, 0x00020003;
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CHECKREG r6, 0x00020003;
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CHECKREG r7, 0x00020003;
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imm32 p2, 0x00040005;
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L0 = P2;
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L1 = P2;
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L2 = P2;
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L3 = P2;
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B0 = P2;
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B1 = P2;
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B2 = P2;
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B3 = P2;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00040005;
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CHECKREG r1, 0x00040005;
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CHECKREG r2, 0x00040005;
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CHECKREG r3, 0x00040005;
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CHECKREG r4, 0x00040005;
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CHECKREG r5, 0x00040005;
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CHECKREG r6, 0x00040005;
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CHECKREG r7, 0x00040005;
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imm32 p3, 0x00060007;
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L0 = P3;
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L1 = P3;
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L2 = P3;
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L3 = P3;
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B0 = P3;
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B1 = P3;
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B2 = P3;
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B3 = P3;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00060007;
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CHECKREG r1, 0x00060007;
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CHECKREG r2, 0x00060007;
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CHECKREG r3, 0x00060007;
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CHECKREG r4, 0x00060007;
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CHECKREG r5, 0x00060007;
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CHECKREG r6, 0x00060007;
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CHECKREG r7, 0x00060007;
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imm32 p4, 0x00080009;
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L0 = P4;
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L1 = P4;
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L2 = P4;
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L3 = P4;
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B0 = P4;
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B1 = P4;
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B2 = P4;
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B3 = P4;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x00080009;
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CHECKREG r1, 0x00080009;
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CHECKREG r2, 0x00080009;
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CHECKREG r3, 0x00080009;
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CHECKREG r4, 0x00080009;
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CHECKREG r5, 0x00080009;
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CHECKREG r6, 0x00080009;
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CHECKREG r7, 0x00080009;
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imm32 p5, 0x000a000b;
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L0 = P5;
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L1 = P5;
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L2 = P5;
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L3 = P5;
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B0 = P5;
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B1 = P5;
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B2 = P5;
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B3 = P5;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x000a000b;
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CHECKREG r1, 0x000a000b;
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CHECKREG r2, 0x000a000b;
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CHECKREG r3, 0x000a000b;
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CHECKREG r4, 0x000a000b;
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CHECKREG r5, 0x000a000b;
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CHECKREG r6, 0x000a000b;
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CHECKREG r7, 0x000a000b;
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imm32 sp, 0x000c000d;
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L0 = SP;
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L1 = SP;
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L2 = SP;
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L3 = SP;
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B0 = SP;
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B1 = SP;
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B2 = SP;
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B3 = SP;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x000c000d;
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CHECKREG r1, 0x000c000d;
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CHECKREG r2, 0x000c000d;
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CHECKREG r3, 0x000c000d;
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CHECKREG r4, 0x000c000d;
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CHECKREG r5, 0x000c000d;
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CHECKREG r6, 0x000c000d;
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CHECKREG r7, 0x000c000d;
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imm32 fp, 0x000e000f;
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L0 = FP;
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L1 = FP;
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L2 = FP;
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L3 = FP;
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B0 = FP;
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B1 = FP;
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B2 = FP;
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B3 = FP;
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R0 = L0;
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R1 = L1;
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R2 = L2;
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R3 = L3;
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R4 = B0;
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R5 = B1;
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R6 = B2;
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R7 = B3;
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CHECKREG r0, 0x000e000f;
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CHECKREG r1, 0x000e000f;
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CHECKREG r2, 0x000e000f;
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CHECKREG r3, 0x000e000f;
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CHECKREG r4, 0x000e000f;
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CHECKREG r5, 0x000e000f;
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CHECKREG r6, 0x000e000f;
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CHECKREG r7, 0x000e000f;
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pass
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