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binutils-gdb/sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s
Mike Frysinger 1368b914e9 sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.
2021-01-15 19:18:34 -05:00

246 lines
6.1 KiB
ArmAsm

//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp
// Spec Reference: dsp32mac pair a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (ISS2);
P1 = A1.w;
A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A1.w;
A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (ISS2);
P3 = A1.w;
A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (ISS2);
P4 = A1.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xF2CF3598;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xEE90C2FC;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0x00DDE22A;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0xFF910EEB;
CHECKREG p2, 0x00025D4F;
CHECKREG p3, 0xFFCD4859;
CHECKREG p4, 0x0E03FC27;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF89EF66E;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0xF8878042;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xFCB93CEB;
CHECKREG p2, 0xFCBB1787;
CHECKREG p3, 0xFC43C021;
CHECKREG p4, 0xFC4F7B37;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
A1 += R6.H * R7.L, R4 = ( A0 -= R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF8876658;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xD26DD7B8;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0xE590030B;
CHECKREG p2, 0x0003178C;
CHECKREG p3, 0xFC43B32C;
CHECKREG p4, 0xE936EBDC;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A0.w;
A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (ISS2);
P2 = A0.w;
A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (ISS2);
P3 = A0.w;
A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0xFF256182;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0xFF1FB35E;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0xF750102E;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0xFFFCF74D;
CHECKREG p2, 0xFF92B0C1;
CHECKREG p3, 0xFF8FD9AF;
CHECKREG p4, 0xFBA80817;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L (M), R6 = ( A0 -= R1.L * R0.L ) (ISS2);
P5 = A1.w;
P1 = A0.w;
A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (ISS2);
P3 = A0.w;
A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xF2CF3598;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xF0DDEE08;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0xF82DF258;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0xFC16F92C;
CHECKREG p2, 0xFFFD9ABC;
CHECKREG p3, 0xF9679ACC;
CHECKREG p4, 0xF86EF704;
CHECKREG p5, 0xFF82C04D;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
R0 = ( A0 -= R2.H * R3.L ) (ISS2);
P2 = A0.w;
R2 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
R0 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF89EF66E;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0xF8878042;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xFCB93CEB;
CHECKREG p2, 0xFCBB1787;
CHECKREG p3, 0xFC43C021;
CHECKREG p4, 0xFC4F7B37;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
R6 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
R4 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF8876658;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x1EA0F4F8;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0xE590030B;
CHECKREG p2, 0x0003178C;
CHECKREG p3, 0xFC43B32C;
CHECKREG p4, 0x0F507A7C;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A0.w;
A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P2 = A0.w;
A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (ISS2);
P3 = A0.w;
R6 = ( A0 += R4.L * R6.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0x00D48D18;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0x00DA3B3C;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0x06E3E0DC;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0xFFFCF74D;
CHECKREG p2, 0x006A468C;
CHECKREG p3, 0x006D1D9E;
CHECKREG p4, 0x0371F06E;
pass