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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
146 lines
3.4 KiB
ArmAsm
146 lines
3.4 KiB
ArmAsm
//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
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// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
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# mach: bfin
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.include "testutils.inc"
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start
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A1 = A0 = 0;
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// The result accumulated in A1 , and stored to a reg half
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imm32 r0, 0xa3545abd;
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imm32 r1, 0xbdbcfec7;
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imm32 r2, 0xc1248679;
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imm32 r3, 0xd0069007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0xcd35500b;
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imm32 r6, 0xe00c800d;
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imm32 r7, 0xf78e900f;
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R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU);
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R1 = A1.w;
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R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU);
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R3 = A1.w;
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R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU);
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R5 = A1.w;
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R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU);
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R7 = A1.w;
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CHECKREG r0, 0x5A4E5ABD;
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CHECKREG r1, 0x5A4E0EEB;
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CHECKREG r2, 0x00008679;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x4AF54569;
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CHECKREG r5, 0x4AF50D14;
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CHECKREG r6, 0xFFFF800D;
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CHECKREG r7, 0x239CE7BC;
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// The result accumulated in A1, and stored to a reg half (MNOP)
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imm32 r0, 0x63548abd;
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imm32 r1, 0x7dbcfec7;
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imm32 r2, 0xC5885679;
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imm32 r3, 0xC5880000;
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imm32 r4, 0xcfbc4569;
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imm32 r5, 0xd235c00b;
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imm32 r6, 0xe00ca00d;
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imm32 r7, 0x678e700f;
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R0.H = ( A1 = R1.L * R0.L ) (TFU);
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R1 = A1.w;
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R2.H = ( A1 += R2.L * R3.H ) (TFU);
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R3 = A1.w;
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R4.H = ( A1 -= R4.H * R5.L ) (TFU);
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R5 = A1.w;
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R6.H = ( A1 = R6.H * R7.H ) (TFU);
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R7 = A1.w;
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CHECKREG r0, 0x8A138ABD;
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CHECKREG r1, 0x8A135EEB;
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CHECKREG r2, 0xCCCC5679;
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CHECKREG r3, 0xCCCC6C33;
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CHECKREG r4, 0x30F64569;
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CHECKREG r5, 0x30F67F1F;
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CHECKREG r6, 0x5AA1A00D;
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CHECKREG r7, 0x5AA11AA8;
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// The result accumulated in A1 , and stored to a reg half (MNOP)
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imm32 r0, 0x5354babd;
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imm32 r1, 0x6dbcdec7;
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imm32 r2, 0x7124e679;
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imm32 r3, 0x80067007;
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imm32 r4, 0x9fbc4569;
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imm32 r5, 0xa235900b;
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imm32 r6, 0xb00c300d;
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imm32 r7, 0xc78ea00f;
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R0.H = A1 , A0 -= R1.L * R0.L (TFU);
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R1 = A1.w;
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R2.H = A1 , A0 += R2.H * R3.L (TFU);
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R3 = A1.w;
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R4.H = A1 , A0 -= R4.H * R5.H (TFU);
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R5 = A1.w;
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R6.H = A1 , A0 = R6.L * R7.H (TFU);
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R7 = A1.w;
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CHECKREG r0, 0x5AA1BABD;
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CHECKREG r1, 0x5AA11AA8;
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CHECKREG r2, 0x5AA1E679;
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CHECKREG r3, 0x5AA11AA8;
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CHECKREG r4, 0x5AA14569;
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CHECKREG r5, 0x5AA11AA8;
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CHECKREG r6, 0x5AA1300D;
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CHECKREG r7, 0x5AA11AA8;
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// The result accumulated in A1 , and stored to a reg half
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imm32 r0, 0x33545abd;
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imm32 r1, 0x5dbcfec7;
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imm32 r2, 0x71245679;
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imm32 r3, 0x90060007;
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imm32 r4, 0xafbc4569;
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imm32 r5, 0xd235900b;
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imm32 r6, 0xc00ca00d;
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imm32 r7, 0x678ed00f;
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R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU);
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R1 = A1.w;
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R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU);
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R3 = A1.w;
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R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU);
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R5 = A1.w;
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R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU);
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R7 = A1.w;
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CHECKREG r0, 0xFF915ABD;
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CHECKREG r1, 0xFF910EEB;
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CHECKREG r2, 0x30375679;
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CHECKREG r3, 0x303725C1;
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CHECKREG r4, 0x5D604569;
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CHECKREG r5, 0x5D60D8AD;
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CHECKREG r6, 0x4382A00D;
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CHECKREG r7, 0x43823355;
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// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
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imm32 r0, 0x92005ABD;
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imm32 r1, 0x09300000;
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imm32 r2, 0x56749679;
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imm32 r3, 0x30A95000;
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imm32 r4, 0xa0009669;
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imm32 r5, 0x01000970;
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imm32 r6, 0xdf45609D;
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imm32 r7, 0x12345679;
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R0.H = ( A1 += R1.L * R0.L ) (M,TFU);
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R1 = A1.w;
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R2.H = ( A1 -= R2.L * R3.H ) (M,TFU);
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R3 = A1.w;
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R4.H = ( A1 = R4.H * R5.L ) (M,TFU);
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R5 = A1.w;
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R6.H = ( A1 -= R6.H * R7.H ) (M,TFU);
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R7 = A1.w;
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CHECKREG r0, 0x43825ABD;
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CHECKREG r1, 0x43823355;
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CHECKREG r2, 0x57919679;
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CHECKREG r3, 0x57912D74;
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CHECKREG r4, 0xFC769669;
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CHECKREG r5, 0xFC760000;
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CHECKREG r6, 0xFEC9609D;
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CHECKREG r7, 0xFEC9CBFC;
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pass
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